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-rw-r--r--target/i386/cpu-qom.h42
-rw-r--r--target/i386/cpu.c9
-rw-r--r--target/i386/cpu.h43
-rw-r--r--target/i386/hvf/hvf.c4
-rw-r--r--target/i386/hvf/x86_emu.c111
-rw-r--r--target/i386/hvf/x86_emu.h4
-rw-r--r--target/i386/kvm/kvm-cpu.c1
-rw-r--r--target/i386/monitor.c5
8 files changed, 110 insertions, 109 deletions
diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h
index 2350f4ae60..d4e216d000 100644
--- a/target/i386/cpu-qom.h
+++ b/target/i386/cpu-qom.h
@@ -21,8 +21,6 @@
#define QEMU_I386_CPU_QOM_H
#include "hw/core/cpu.h"
-#include "qemu/notify.h"
-#include "qom/object.h"
#ifdef TARGET_X86_64
#define TYPE_X86_CPU "x86_64-cpu"
@@ -32,43 +30,7 @@
OBJECT_DECLARE_CPU_TYPE(X86CPU, X86CPUClass, X86_CPU)
-typedef struct X86CPUModel X86CPUModel;
-
-/**
- * X86CPUClass:
- * @cpu_def: CPU model definition
- * @host_cpuid_required: Whether CPU model requires cpuid from host.
- * @ordering: Ordering on the "-cpu help" CPU model list.
- * @migration_safe: See CpuDefinitionInfo::migration_safe
- * @static_model: See CpuDefinitionInfo::static
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- *
- * An x86 CPU model or family.
- */
-struct X86CPUClass {
- /*< private >*/
- CPUClass parent_class;
- /*< public >*/
-
- /* CPU definition, automatically loaded by instance_init if not NULL.
- * Should be eventually replaced by subclass-specific property defaults.
- */
- X86CPUModel *model;
-
- bool host_cpuid_required;
- int ordering;
- bool migration_safe;
- bool static_model;
-
- /* Optional description of CPU model.
- * If unavailable, cpu_def->model_id is used */
- const char *model_description;
-
- DeviceRealize parent_realize;
- DeviceUnrealize parent_unrealize;
- ResettablePhases parent_phases;
-};
-
+#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
+#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
#endif
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index fc8484cb5e..358d9c0a65 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6019,7 +6019,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
X86CPUTopoInfo topo_info;
topo_info.dies_per_pkg = env->nr_dies;
- topo_info.cores_per_die = cs->nr_cores;
+ topo_info.cores_per_die = cs->nr_cores / env->nr_dies;
topo_info.threads_per_core = cs->nr_threads;
/* Calculate & apply limits for different index ranges */
@@ -6095,8 +6095,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
*/
if (*eax & 31) {
int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14);
- int vcpus_per_socket = env->nr_dies * cs->nr_cores *
- cs->nr_threads;
+ int vcpus_per_socket = cs->nr_cores * cs->nr_threads;
if (cs->nr_cores > 1) {
*eax &= ~0xFC000000;
*eax |= (pow2ceil(cs->nr_cores) - 1) << 26;
@@ -6273,12 +6272,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
break;
case 1:
*eax = apicid_die_offset(&topo_info);
- *ebx = cs->nr_cores * cs->nr_threads;
+ *ebx = topo_info.cores_per_die * topo_info.threads_per_core;
*ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
break;
case 2:
*eax = apicid_pkg_offset(&topo_info);
- *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
+ *ebx = cs->nr_cores * cs->nr_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
break;
default:
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 471e71dbc5..cd2e295bd6 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1882,6 +1882,7 @@ typedef struct CPUArchState {
TPRAccess tpr_access_type;
+ /* Number of dies within this CPU package. */
unsigned nr_dies;
} CPUX86State;
@@ -1897,9 +1898,7 @@ struct kvm_msrs;
* An x86 CPU.
*/
struct ArchCPU {
- /*< private >*/
CPUState parent_obj;
- /*< public >*/
CPUX86State env;
VMChangeStateEntry *vmsentry;
@@ -2039,6 +2038,44 @@ struct ArchCPU {
bool xen_vapic;
};
+typedef struct X86CPUModel X86CPUModel;
+
+/**
+ * X86CPUClass:
+ * @cpu_def: CPU model definition
+ * @host_cpuid_required: Whether CPU model requires cpuid from host.
+ * @ordering: Ordering on the "-cpu help" CPU model list.
+ * @migration_safe: See CpuDefinitionInfo::migration_safe
+ * @static_model: See CpuDefinitionInfo::static
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ *
+ * An x86 CPU model or family.
+ */
+struct X86CPUClass {
+ CPUClass parent_class;
+
+ /*
+ * CPU definition, automatically loaded by instance_init if not NULL.
+ * Should be eventually replaced by subclass-specific property defaults.
+ */
+ X86CPUModel *model;
+
+ bool host_cpuid_required;
+ int ordering;
+ bool migration_safe;
+ bool static_model;
+
+ /*
+ * Optional description of CPU model.
+ * If unavailable, cpu_def->model_id is used.
+ */
+ const char *model_description;
+
+ DeviceRealize parent_realize;
+ DeviceUnrealize parent_unrealize;
+ ResettablePhases parent_phases;
+};
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_x86_cpu;
@@ -2241,8 +2278,6 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
/* hw/pc.c */
uint64_t cpu_get_tsc(CPUX86State *env);
-#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
-#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
#define CPU_RESOLVING_TYPE TYPE_X86_CPU
#ifdef TARGET_X86_64
diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c
index cb2cd0b02f..20b9ca3ef5 100644
--- a/target/i386/hvf/hvf.c
+++ b/target/i386/hvf/hvf.c
@@ -591,9 +591,9 @@ int hvf_vcpu_exec(CPUState *cpu)
{
load_regs(cpu);
if (exit_reason == EXIT_REASON_RDMSR) {
- simulate_rdmsr(cpu);
+ simulate_rdmsr(env);
} else {
- simulate_wrmsr(cpu);
+ simulate_wrmsr(env);
}
env->eip += ins_len;
store_regs(cpu);
diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c
index ccda568478..3a3f0a50d0 100644
--- a/target/i386/hvf/x86_emu.c
+++ b/target/i386/hvf/x86_emu.c
@@ -45,7 +45,7 @@
#include "vmcs.h"
#include "vmx.h"
-void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data,
+void hvf_handle_io(CPUState *cs, uint16_t port, void *data,
int direction, int size, uint32_t count);
#define EXEC_2OP_FLAGS_CMD(env, decode, cmd, FLAGS_FUNC, save_res) \
@@ -663,35 +663,34 @@ static void exec_lods(CPUX86State *env, struct x86_decode *decode)
env->eip += decode->len;
}
-void simulate_rdmsr(struct CPUState *cpu)
+void simulate_rdmsr(CPUX86State *env)
{
- X86CPU *x86_cpu = X86_CPU(cpu);
- CPUX86State *env = &x86_cpu->env;
+ X86CPU *cpu = env_archcpu(env);
CPUState *cs = env_cpu(env);
uint32_t msr = ECX(env);
uint64_t val = 0;
switch (msr) {
case MSR_IA32_TSC:
- val = rdtscp() + rvmcs(cpu->accel->fd, VMCS_TSC_OFFSET);
+ val = rdtscp() + rvmcs(cs->accel->fd, VMCS_TSC_OFFSET);
break;
case MSR_IA32_APICBASE:
- val = cpu_get_apic_base(X86_CPU(cpu)->apic_state);
+ val = cpu_get_apic_base(cpu->apic_state);
break;
case MSR_IA32_UCODE_REV:
- val = x86_cpu->ucode_rev;
+ val = cpu->ucode_rev;
break;
case MSR_EFER:
- val = rvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER);
+ val = rvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER);
break;
case MSR_FSBASE:
- val = rvmcs(cpu->accel->fd, VMCS_GUEST_FS_BASE);
+ val = rvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE);
break;
case MSR_GSBASE:
- val = rvmcs(cpu->accel->fd, VMCS_GUEST_GS_BASE);
+ val = rvmcs(cs->accel->fd, VMCS_GUEST_GS_BASE);
break;
case MSR_KERNELGSBASE:
- val = rvmcs(cpu->accel->fd, VMCS_HOST_FS_BASE);
+ val = rvmcs(cs->accel->fd, VMCS_HOST_FS_BASE);
break;
case MSR_STAR:
abort();
@@ -746,7 +745,7 @@ void simulate_rdmsr(struct CPUState *cpu)
val = env->mtrr_deftype;
break;
case MSR_CORE_THREAD_COUNT:
- val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */
+ val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */
val |= ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */
break;
default:
@@ -761,14 +760,14 @@ void simulate_rdmsr(struct CPUState *cpu)
static void exec_rdmsr(CPUX86State *env, struct x86_decode *decode)
{
- simulate_rdmsr(env_cpu(env));
+ simulate_rdmsr(env);
env->eip += decode->len;
}
-void simulate_wrmsr(struct CPUState *cpu)
+void simulate_wrmsr(CPUX86State *env)
{
- X86CPU *x86_cpu = X86_CPU(cpu);
- CPUX86State *env = &x86_cpu->env;
+ X86CPU *cpu = env_archcpu(env);
+ CPUState *cs = env_cpu(env);
uint32_t msr = ECX(env);
uint64_t data = ((uint64_t)EDX(env) << 32) | EAX(env);
@@ -776,16 +775,16 @@ void simulate_wrmsr(struct CPUState *cpu)
case MSR_IA32_TSC:
break;
case MSR_IA32_APICBASE:
- cpu_set_apic_base(X86_CPU(cpu)->apic_state, data);
+ cpu_set_apic_base(cpu->apic_state, data);
break;
case MSR_FSBASE:
- wvmcs(cpu->accel->fd, VMCS_GUEST_FS_BASE, data);
+ wvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE, data);
break;
case MSR_GSBASE:
- wvmcs(cpu->accel->fd, VMCS_GUEST_GS_BASE, data);
+ wvmcs(cs->accel->fd, VMCS_GUEST_GS_BASE, data);
break;
case MSR_KERNELGSBASE:
- wvmcs(cpu->accel->fd, VMCS_HOST_FS_BASE, data);
+ wvmcs(cs->accel->fd, VMCS_HOST_FS_BASE, data);
break;
case MSR_STAR:
abort();
@@ -797,10 +796,10 @@ void simulate_wrmsr(struct CPUState *cpu)
abort();
break;
case MSR_EFER:
- /*printf("new efer %llx\n", EFER(cpu));*/
- wvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER, data);
+ /*printf("new efer %llx\n", EFER(cs));*/
+ wvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER, data);
if (data & MSR_EFER_NXE) {
- hv_vcpu_invalidate_tlb(cpu->accel->fd);
+ hv_vcpu_invalidate_tlb(cs->accel->fd);
}
break;
case MSR_MTRRphysBase(0):
@@ -849,14 +848,14 @@ void simulate_wrmsr(struct CPUState *cpu)
/* Related to support known hypervisor interface */
/* if (g_hypervisor_iface)
- g_hypervisor_iface->wrmsr_handler(cpu, msr, data);
+ g_hypervisor_iface->wrmsr_handler(cs, msr, data);
- printf("write msr %llx\n", RCX(cpu));*/
+ printf("write msr %llx\n", RCX(cs));*/
}
static void exec_wrmsr(CPUX86State *env, struct x86_decode *decode)
{
- simulate_wrmsr(env_cpu(env));
+ simulate_wrmsr(env);
env->eip += decode->len;
}
@@ -1418,56 +1417,56 @@ static void init_cmd_handler()
}
}
-void load_regs(struct CPUState *cpu)
+void load_regs(CPUState *cs)
{
- X86CPU *x86_cpu = X86_CPU(cpu);
- CPUX86State *env = &x86_cpu->env;
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
int i = 0;
- RRX(env, R_EAX) = rreg(cpu->accel->fd, HV_X86_RAX);
- RRX(env, R_EBX) = rreg(cpu->accel->fd, HV_X86_RBX);
- RRX(env, R_ECX) = rreg(cpu->accel->fd, HV_X86_RCX);
- RRX(env, R_EDX) = rreg(cpu->accel->fd, HV_X86_RDX);
- RRX(env, R_ESI) = rreg(cpu->accel->fd, HV_X86_RSI);
- RRX(env, R_EDI) = rreg(cpu->accel->fd, HV_X86_RDI);
- RRX(env, R_ESP) = rreg(cpu->accel->fd, HV_X86_RSP);
- RRX(env, R_EBP) = rreg(cpu->accel->fd, HV_X86_RBP);
+ RRX(env, R_EAX) = rreg(cs->accel->fd, HV_X86_RAX);
+ RRX(env, R_EBX) = rreg(cs->accel->fd, HV_X86_RBX);
+ RRX(env, R_ECX) = rreg(cs->accel->fd, HV_X86_RCX);
+ RRX(env, R_EDX) = rreg(cs->accel->fd, HV_X86_RDX);
+ RRX(env, R_ESI) = rreg(cs->accel->fd, HV_X86_RSI);
+ RRX(env, R_EDI) = rreg(cs->accel->fd, HV_X86_RDI);
+ RRX(env, R_ESP) = rreg(cs->accel->fd, HV_X86_RSP);
+ RRX(env, R_EBP) = rreg(cs->accel->fd, HV_X86_RBP);
for (i = 8; i < 16; i++) {
- RRX(env, i) = rreg(cpu->accel->fd, HV_X86_RAX + i);
+ RRX(env, i) = rreg(cs->accel->fd, HV_X86_RAX + i);
}
- env->eflags = rreg(cpu->accel->fd, HV_X86_RFLAGS);
+ env->eflags = rreg(cs->accel->fd, HV_X86_RFLAGS);
rflags_to_lflags(env);
- env->eip = rreg(cpu->accel->fd, HV_X86_RIP);
+ env->eip = rreg(cs->accel->fd, HV_X86_RIP);
}
-void store_regs(struct CPUState *cpu)
+void store_regs(CPUState *cs)
{
- X86CPU *x86_cpu = X86_CPU(cpu);
- CPUX86State *env = &x86_cpu->env;
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
int i = 0;
- wreg(cpu->accel->fd, HV_X86_RAX, RAX(env));
- wreg(cpu->accel->fd, HV_X86_RBX, RBX(env));
- wreg(cpu->accel->fd, HV_X86_RCX, RCX(env));
- wreg(cpu->accel->fd, HV_X86_RDX, RDX(env));
- wreg(cpu->accel->fd, HV_X86_RSI, RSI(env));
- wreg(cpu->accel->fd, HV_X86_RDI, RDI(env));
- wreg(cpu->accel->fd, HV_X86_RBP, RBP(env));
- wreg(cpu->accel->fd, HV_X86_RSP, RSP(env));
+ wreg(cs->accel->fd, HV_X86_RAX, RAX(env));
+ wreg(cs->accel->fd, HV_X86_RBX, RBX(env));
+ wreg(cs->accel->fd, HV_X86_RCX, RCX(env));
+ wreg(cs->accel->fd, HV_X86_RDX, RDX(env));
+ wreg(cs->accel->fd, HV_X86_RSI, RSI(env));
+ wreg(cs->accel->fd, HV_X86_RDI, RDI(env));
+ wreg(cs->accel->fd, HV_X86_RBP, RBP(env));
+ wreg(cs->accel->fd, HV_X86_RSP, RSP(env));
for (i = 8; i < 16; i++) {
- wreg(cpu->accel->fd, HV_X86_RAX + i, RRX(env, i));
+ wreg(cs->accel->fd, HV_X86_RAX + i, RRX(env, i));
}
lflags_to_rflags(env);
- wreg(cpu->accel->fd, HV_X86_RFLAGS, env->eflags);
- macvm_set_rip(cpu, env->eip);
+ wreg(cs->accel->fd, HV_X86_RFLAGS, env->eflags);
+ macvm_set_rip(cs, env->eip);
}
bool exec_instruction(CPUX86State *env, struct x86_decode *ins)
{
- /*if (hvf_vcpu_id(cpu))
- printf("%d, %llx: exec_instruction %s\n", hvf_vcpu_id(cpu), env->eip,
+ /*if (hvf_vcpu_id(cs))
+ printf("%d, %llx: exec_instruction %s\n", hvf_vcpu_id(cs), env->eip,
decode_cmd_to_string(ins->cmd));*/
if (!_cmd_handler[ins->cmd].handler) {
diff --git a/target/i386/hvf/x86_emu.h b/target/i386/hvf/x86_emu.h
index 640da90b30..4b846ba80e 100644
--- a/target/i386/hvf/x86_emu.h
+++ b/target/i386/hvf/x86_emu.h
@@ -29,8 +29,8 @@ bool exec_instruction(CPUX86State *env, struct x86_decode *ins);
void load_regs(struct CPUState *cpu);
void store_regs(struct CPUState *cpu);
-void simulate_rdmsr(struct CPUState *cpu);
-void simulate_wrmsr(struct CPUState *cpu);
+void simulate_rdmsr(CPUX86State *env);
+void simulate_wrmsr(CPUX86State *env);
target_ulong read_reg(CPUX86State *env, int reg, int size);
void write_reg(CPUX86State *env, int reg, target_ulong val, int size);
diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c
index 56c72f3c45..9c791b7b05 100644
--- a/target/i386/kvm/kvm-cpu.c
+++ b/target/i386/kvm/kvm-cpu.c
@@ -37,6 +37,7 @@ static bool kvm_cpu_realizefn(CPUState *cs, Error **errp)
* -> cpu_exec_realizefn():
* -> accel_cpu_common_realize()
* kvm_cpu_realizefn() -> host_cpu_realizefn()
+ * -> cpu_common_realizefn()
* -> check/update ucode_rev, phys_bits, mwait
*/
if (cpu->max_features) {
diff --git a/target/i386/monitor.c b/target/i386/monitor.c
index 6512846327..950ff9ccbc 100644
--- a/target/i386/monitor.c
+++ b/target/i386/monitor.c
@@ -28,6 +28,7 @@
#include "monitor/hmp-target.h"
#include "monitor/hmp.h"
#include "qapi/qmp/qdict.h"
+#include "sysemu/hw_accel.h"
#include "sysemu/kvm.h"
#include "qapi/error.h"
#include "qapi/qapi-commands-misc-target.h"
@@ -654,7 +655,11 @@ void hmp_info_local_apic(Monitor *mon, const QDict *qdict)
if (qdict_haskey(qdict, "apic-id")) {
int id = qdict_get_try_int(qdict, "apic-id", 0);
+
cs = cpu_by_arch_id(id);
+ if (cs) {
+ cpu_synchronize_state(cs);
+ }
} else {
cs = mon_get_cpu(mon);
}
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-07 20:22:00 +0000