diff options
Diffstat (limited to 'target/i386/tcg/translate.c')
| -rw-r--r-- | target/i386/tcg/translate.c | 27 |
1 files changed, 19 insertions, 8 deletions
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index b72864bf01..98f5fe61ed 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -304,6 +304,7 @@ static const uint8_t cc_op_live[CC_OP_NB] = { [CC_OP_SHLB ... CC_OP_SHLQ] = USES_CC_DST | USES_CC_SRC, [CC_OP_SARB ... CC_OP_SARQ] = USES_CC_DST | USES_CC_SRC, [CC_OP_BMILGB ... CC_OP_BMILGQ] = USES_CC_DST | USES_CC_SRC, + [CC_OP_BLSIB ... CC_OP_BLSIQ] = USES_CC_DST | USES_CC_SRC, [CC_OP_ADCX] = USES_CC_DST | USES_CC_SRC, [CC_OP_ADOX] = USES_CC_SRC | USES_CC_SRC2, [CC_OP_ADCOX] = USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, @@ -865,6 +866,18 @@ static CCPrepare gen_prepare_sign_nz(TCGv src, MemOp size) } } +static CCPrepare gen_prepare_val_nz(TCGv src, MemOp size, bool eqz) +{ + if (size == MO_TL) { + return (CCPrepare) { .cond = eqz ? TCG_COND_EQ : TCG_COND_NE, + .reg = src }; + } else { + return (CCPrepare) { .cond = eqz ? TCG_COND_TSTEQ : TCG_COND_TSTNE, + .imm = MAKE_64BIT_MASK(0, 8 << size), + .reg = src }; + } +} + /* compute eflags.C, trying to store it in reg if not NULL */ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg) { @@ -908,8 +921,11 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg) case CC_OP_BMILGB ... CC_OP_BMILGQ: size = s->cc_op - CC_OP_BMILGB; - gen_ext_tl(cpu_cc_src, cpu_cc_src, size, false); - return (CCPrepare) { .cond = TCG_COND_EQ, .reg = cpu_cc_src }; + return gen_prepare_val_nz(cpu_cc_src, size, true); + + case CC_OP_BLSIB ... CC_OP_BLSIQ: + size = s->cc_op - CC_OP_BLSIB; + return gen_prepare_val_nz(cpu_cc_src, size, false); case CC_OP_ADCX: case CC_OP_ADCOX: @@ -1006,12 +1022,7 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg) default: { MemOp size = (s->cc_op - CC_OP_ADDB) & 3; - if (size == MO_TL) { - return (CCPrepare) { .cond = TCG_COND_EQ, .reg = cpu_cc_dst }; - } else { - return (CCPrepare) { .cond = TCG_COND_TSTEQ, .reg = cpu_cc_dst, - .imm = (1ull << (8 << size)) - 1 }; - } + return gen_prepare_val_nz(cpu_cc_dst, size, true); } } } |