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-rw-r--r--target/arm/arch_dump.c11
-rw-r--r--target/arm/cpu.c4
-rw-r--r--target/arm/cpu.h9
-rw-r--r--target/arm/helper.c4
-rw-r--r--target/arm/m_helper.c11
5 files changed, 25 insertions, 14 deletions
diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c
index 2345dec3c2..7693e17e96 100644
--- a/target/arm/arch_dump.c
+++ b/target/arm/arch_dump.c
@@ -363,9 +363,11 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, void *opaque)
{
struct arm_note note;
- CPUARMState *env = &ARM_CPU(cs)->env;
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
DumpState *s = opaque;
- int ret, i, fpvalid = !!arm_feature(env, ARM_FEATURE_VFP);
+ int ret, i;
+ bool fpvalid = cpu_isar_feature(aa32_vfp_simd, cpu);
arm_note_init(&note, s, "CORE", 5, NT_PRSTATUS, sizeof(note.prstatus));
@@ -444,7 +446,6 @@ int cpu_get_dump_info(ArchDumpInfo *info,
ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
{
ARMCPU *cpu = ARM_CPU(first_cpu);
- CPUARMState *env = &cpu->env;
size_t note_size;
if (class == ELFCLASS64) {
@@ -452,12 +453,12 @@ ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
note_size += AARCH64_PRFPREG_NOTE_SIZE;
#ifdef TARGET_AARCH64
if (cpu_isar_feature(aa64_sve, cpu)) {
- note_size += AARCH64_SVE_NOTE_SIZE(env);
+ note_size += AARCH64_SVE_NOTE_SIZE(&cpu->env);
}
#endif
} else {
note_size = ARM_PRSTATUS_NOTE_SIZE;
- if (arm_feature(env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
note_size += ARM_VFP_NOTE_SIZE;
}
}
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 2eadf4dcb8..be4c2a1253 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -293,7 +293,7 @@ static void arm_cpu_reset(CPUState *s)
env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
}
- if (arm_feature(env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK;
env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK |
R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK;
@@ -1011,7 +1011,7 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
int numvfpregs = 0;
if (cpu_isar_feature(aa32_simd_r32, cpu)) {
numvfpregs = 32;
- } else if (arm_feature(env, ARM_FEATURE_VFP)) {
+ } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
numvfpregs = 16;
}
for (i = 0; i < numvfpregs; i++) {
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 65171cb30e..a128d48d40 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3450,6 +3450,15 @@ static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
}
+static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
+{
+ /*
+ * Return true if either VFP or SIMD is implemented.
+ * In this case, a minimum of VFP w/ D0-D15.
+ */
+ return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0;
+}
+
static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id)
{
/* Return true if D16-D31 are implemented */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 79db169e04..8841cc7fde 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -894,7 +894,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
* ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
* TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
*/
- if (arm_feature(env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
/* VFP coprocessor: cp10 & cp11 [23:20] */
mask |= (1 << 31) | (1 << 30) | (0xf << 20);
@@ -7814,7 +7814,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
} else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
35, "arm-vfp3.xml", 0);
- } else if (arm_feature(env, ARM_FEATURE_VFP)) {
+ } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
19, "arm-vfp.xml", 0);
}
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index 33d414a684..5e8a795d20 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -738,7 +738,8 @@ static uint32_t v7m_integrity_sig(CPUARMState *env, uint32_t lr)
*/
uint32_t sig = 0xfefa125a;
- if (!arm_feature(env, ARM_FEATURE_VFP) || (lr & R_V7M_EXCRET_FTYPE_MASK)) {
+ if (!cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))
+ || (lr & R_V7M_EXCRET_FTYPE_MASK)) {
sig |= 1;
}
return sig;
@@ -841,7 +842,7 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
if (dotailchain) {
/* Sanitize LR FType and PREFIX bits */
- if (!arm_feature(env, ARM_FEATURE_VFP)) {
+ if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
lr |= R_V7M_EXCRET_FTYPE_MASK;
}
lr = deposit32(lr, 24, 8, 0xff);
@@ -1373,7 +1374,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
ftype = excret & R_V7M_EXCRET_FTYPE_MASK;
- if (!arm_feature(env, ARM_FEATURE_VFP) && !ftype) {
+ if (!ftype && !cpu_isar_feature(aa32_vfp_simd, cpu)) {
qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero FTYPE in exception "
"exit PC value 0x%" PRIx32 " is UNPREDICTABLE "
"if FPU not present\n",
@@ -2450,7 +2451,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
* SFPA is RAZ/WI from NS. FPCA is RO if NSACR.CP10 == 0,
* RES0 if the FPU is not present, and is stored in the S bank
*/
- if (arm_feature(env, ARM_FEATURE_VFP) &&
+ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env)) &&
extract32(env->v7m.nsacr, 10, 1)) {
env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_FPCA_MASK;
env->v7m.control[M_REG_S] |= val & R_V7M_CONTROL_FPCA_MASK;
@@ -2565,7 +2566,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK;
env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK;
}
- if (arm_feature(env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
/*
* SFPA is RAZ/WI from NS or if no FPU.
* FPCA is RO if NSACR.CP10 == 0, RES0 if the FPU is not present.
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-19 23:18:22 +0000