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-rw-r--r--target/arm/translate.c38
1 files changed, 38 insertions, 0 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 9f2b6018a2..47a1a5739c 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7968,6 +7968,44 @@ static bool trans_LDM_t16(DisasContext *s, arg_ldst_block *a)
return do_ldm(s, a, 1);
}
+static bool trans_CLRM(DisasContext *s, arg_CLRM *a)
+{
+ int i;
+ TCGv_i32 zero;
+
+ if (!dc_isar_feature(aa32_m_sec_state, s)) {
+ return false;
+ }
+
+ if (extract32(a->list, 13, 1)) {
+ return false;
+ }
+
+ if (!a->list) {
+ /* UNPREDICTABLE; we choose to UNDEF */
+ return false;
+ }
+
+ zero = tcg_const_i32(0);
+ for (i = 0; i < 15; i++) {
+ if (extract32(a->list, i, 1)) {
+ /* Clear R[i] */
+ tcg_gen_mov_i32(cpu_R[i], zero);
+ }
+ }
+ if (extract32(a->list, 15, 1)) {
+ /*
+ * Clear APSR (by calling the MSR helper with the same argument
+ * as for "MSR APSR_nzcvqg, Rn": mask = 0b1100, SYSM=0)
+ */
+ TCGv_i32 maskreg = tcg_const_i32(0xc << 8);
+ gen_helper_v7m_msr(cpu_env, maskreg, zero);
+ tcg_temp_free_i32(maskreg);
+ }
+ tcg_temp_free_i32(zero);
+ return true;
+}
+
/*
* Branch, branch with link
*/