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Diffstat (limited to 'hw/sparc/leon3.c')
-rw-r--r--hw/sparc/leon3.c144
1 files changed, 100 insertions, 44 deletions
diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c
index 2dfb742566..4873b59b6c 100644
--- a/hw/sparc/leon3.c
+++ b/hw/sparc/leon3.c
@@ -1,7 +1,9 @@
/*
* QEMU Leon3 System Emulator
*
- * Copyright (c) 2010-2019 AdaCore
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright (c) 2010-2024 AdaCore
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -40,7 +42,9 @@
#include "elf.h"
#include "trace.h"
-#include "hw/sparc/grlib.h"
+#include "hw/timer/grlib_gptimer.h"
+#include "hw/char/grlib_uart.h"
+#include "hw/intc/grlib_irqmp.h"
#include "hw/misc/grlib_ahb_apb_pnp.h"
/* Default system clock. */
@@ -50,6 +54,8 @@
#define LEON3_PROM_OFFSET (0x00000000)
#define LEON3_RAM_OFFSET (0x40000000)
+#define MAX_CPUS 4
+
#define LEON3_UART_OFFSET (0x80000100)
#define LEON3_UART_IRQ (3)
@@ -63,9 +69,11 @@
#define LEON3_AHB_PNP_OFFSET (0xFFFFF000)
typedef struct ResetData {
- SPARCCPU *cpu;
- uint32_t entry; /* save kernel entry in case of reset */
- target_ulong sp; /* initial stack pointer */
+ struct CPUResetData {
+ int id;
+ SPARCCPU *cpu;
+ } info[MAX_CPUS];
+ uint32_t entry; /* save kernel entry in case of reset */
} ResetData;
static uint32_t *gen_store_u32(uint32_t *code, hwaddr addr, uint32_t val)
@@ -91,13 +99,26 @@ static uint32_t *gen_store_u32(uint32_t *code, hwaddr addr, uint32_t val)
/*
* When loading a kernel in RAM the machine is expected to be in a different
- * state (eg: initialized by the bootloader). This little code reproduces
- * this behavior.
+ * state (eg: initialized by the bootloader). This little code reproduces
+ * this behavior. Also this code can be executed by the secondary cpus as
+ * well since it looks at the %asr17 register before doing any
+ * initialization, it allows to use the same reset address for all the
+ * cpus.
*/
-static void write_bootloader(CPUSPARCState *env, uint8_t *base,
- hwaddr kernel_addr)
+static void write_bootloader(void *ptr, hwaddr kernel_addr)
{
- uint32_t *p = (uint32_t *) base;
+ uint32_t *p = ptr;
+ uint32_t *sec_cpu_branch_p = NULL;
+
+ /* If we are running on a secondary CPU, jump directly to the kernel. */
+
+ stl_p(p++, 0x85444000); /* rd %asr17, %g2 */
+ stl_p(p++, 0x8530a01c); /* srl %g2, 0x1c, %g2 */
+ stl_p(p++, 0x80908000); /* tst %g2 */
+ /* Filled below. */
+ sec_cpu_branch_p = p;
+ stl_p(p++, 0x0BADC0DE); /* bne xxx */
+ stl_p(p++, 0x01000000); /* nop */
/* Initialize the UARTs */
/* *UART_CONTROL = UART_RECEIVE_ENABLE | UART_TRANSMIT_ENABLE; */
@@ -111,6 +132,10 @@ static void write_bootloader(CPUSPARCState *env, uint8_t *base,
/* *GPTIMER0_CONFIG = GPTIMER_ENABLE | GPTIMER_RESTART; */
p = gen_store_u32(p, 0x80000318, 3);
+ /* Now, the relative branch above can be computed. */
+ stl_p(sec_cpu_branch_p, 0x12800000
+ + (p - sec_cpu_branch_p));
+
/* JUMP to the entry point */
stl_p(p++, 0x82100000); /* mov %g0, %g1 */
stl_p(p++, 0x03000000 + extract32(kernel_addr, 10, 22));
@@ -121,18 +146,19 @@ static void write_bootloader(CPUSPARCState *env, uint8_t *base,
stl_p(p++, 0x01000000); /* nop */
}
-static void main_cpu_reset(void *opaque)
+static void leon3_cpu_reset(void *opaque)
{
- ResetData *s = (ResetData *)opaque;
- CPUState *cpu = CPU(s->cpu);
- CPUSPARCState *env = &s->cpu->env;
+ struct CPUResetData *info = (struct CPUResetData *) opaque;
+ int id = info->id;
+ ResetData *s = (ResetData *)DO_UPCAST(ResetData, info[id], info);
+ CPUState *cpu = CPU(s->info[id].cpu);
+ CPUSPARCState *env = cpu_env(cpu);
cpu_reset(cpu);
- cpu->halted = 0;
- env->pc = s->entry;
- env->npc = s->entry + 4;
- env->regbase[6] = s->sp;
+ cpu->halted = cpu->cpu_index != 0;
+ env->pc = s->entry;
+ env->npc = s->entry + 4;
}
static void leon3_cache_control_int(CPUSPARCState *env)
@@ -166,7 +192,8 @@ static void leon3_cache_control_int(CPUSPARCState *env)
static void leon3_irq_ack(CPUSPARCState *env, int intno)
{
- grlib_irqmp_ack(env->irq_manager, intno);
+ CPUState *cpu = CPU(env_cpu(env));
+ grlib_irqmp_ack(env->irq_manager, cpu->cpu_index, intno);
}
/*
@@ -175,9 +202,10 @@ static void leon3_irq_ack(CPUSPARCState *env, int intno)
*/
static void leon3_set_pil_in(void *opaque, int n, int level)
{
- CPUSPARCState *env = opaque;
+ DeviceState *cpu = opaque;
+ CPUState *cs = CPU(cpu);
+ CPUSPARCState *env = cpu_env(cs);
uint32_t pil_in = level;
- CPUState *cs;
assert(env != NULL);
@@ -193,7 +221,6 @@ static void leon3_set_pil_in(void *opaque, int n, int level)
env->interrupt_index = TT_EXTINT | i;
if (old_interrupt != env->interrupt_index) {
- cs = env_cpu(env);
trace_leon3_set_irq(i);
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
}
@@ -201,13 +228,26 @@ static void leon3_set_pil_in(void *opaque, int n, int level)
}
}
} else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
- cs = env_cpu(env);
trace_leon3_reset_irq(env->interrupt_index & 15);
env->interrupt_index = 0;
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
+static void leon3_start_cpu_async_work(CPUState *cpu, run_on_cpu_data data)
+{
+ cpu->halted = 0;
+}
+
+static void leon3_start_cpu(void *opaque, int n, int level)
+{
+ DeviceState *cpu = opaque;
+ CPUState *cs = CPU(cpu);
+
+ assert(level == 1);
+ async_run_on_cpu(cs, leon3_start_cpu_async_work, RUN_ON_CPU_NULL);
+}
+
static void leon3_irq_manager(CPUSPARCState *env, int intno)
{
leon3_irq_ack(env, intno);
@@ -233,17 +273,23 @@ static void leon3_generic_hw_init(MachineState *machine)
AHBPnp *ahb_pnp;
APBPnp *apb_pnp;
- /* Init CPU */
- cpu = SPARC_CPU(cpu_create(machine->cpu_type));
- env = &cpu->env;
+ reset_info = g_malloc0(sizeof(ResetData));
+
+ for (i = 0; i < machine->smp.cpus; i++) {
+ /* Init CPU */
+ cpu = SPARC_CPU(object_new(machine->cpu_type));
+ qdev_init_gpio_in_named(DEVICE(cpu), leon3_start_cpu, "start_cpu", 1);
+ qdev_init_gpio_in_named(DEVICE(cpu), leon3_set_pil_in, "pil", 1);
+ qdev_realize(DEVICE(cpu), NULL, &error_fatal);
+ env = &cpu->env;
- cpu_sparc_set_id(env, 0);
+ cpu_sparc_set_id(env, i);
- /* Reset data */
- reset_info = g_new0(ResetData, 1);
- reset_info->cpu = cpu;
- reset_info->sp = LEON3_RAM_OFFSET + ram_size;
- qemu_register_reset(main_cpu_reset, reset_info);
+ /* Reset data */
+ reset_info->info[i].id = i;
+ reset_info->info[i].cpu = cpu;
+ qemu_register_reset(leon3_cpu_reset, &reset_info->info[i]);
+ }
ahb_pnp = GRLIB_AHB_PNP(qdev_new(TYPE_GRLIB_AHB_PNP));
sysbus_realize_and_unref(SYS_BUS_DEVICE(ahb_pnp), &error_fatal);
@@ -261,14 +307,24 @@ static void leon3_generic_hw_init(MachineState *machine)
/* Allocate IRQ manager */
irqmpdev = qdev_new(TYPE_GRLIB_IRQMP);
- qdev_init_gpio_in_named_with_opaque(DEVICE(cpu), leon3_set_pil_in,
- env, "pil", 1);
- qdev_connect_gpio_out_named(irqmpdev, "grlib-irq", 0,
- qdev_get_gpio_in_named(DEVICE(cpu), "pil", 0));
+ object_property_set_int(OBJECT(irqmpdev), "ncpus", machine->smp.cpus,
+ &error_fatal);
sysbus_realize_and_unref(SYS_BUS_DEVICE(irqmpdev), &error_fatal);
+
+ for (i = 0; i < machine->smp.cpus; i++) {
+ cpu = reset_info->info[i].cpu;
+ env = &cpu->env;
+ qdev_connect_gpio_out_named(irqmpdev, "grlib-start-cpu", i,
+ qdev_get_gpio_in_named(DEVICE(cpu),
+ "start_cpu", 0));
+ qdev_connect_gpio_out_named(irqmpdev, "grlib-irq", i,
+ qdev_get_gpio_in_named(DEVICE(cpu),
+ "pil", 0));
+ env->irq_manager = irqmpdev;
+ env->qemu_irq_ack = leon3_irq_manager;
+ }
+
sysbus_mmio_map(SYS_BUS_DEVICE(irqmpdev), 0, LEON3_IRQMP_OFFSET);
- env->irq_manager = irqmpdev;
- env->qemu_irq_ack = leon3_irq_manager;
grlib_apb_pnp_add_entry(apb_pnp, LEON3_IRQMP_OFFSET, 0xFFF,
GRLIB_VENDOR_GAISLER, GRLIB_IRQMP_DEV,
2, 0, GRLIB_APBIO_AREA);
@@ -339,13 +395,12 @@ static void leon3_generic_hw_init(MachineState *machine)
* the machine in an initialized state through a little
* bootloader.
*/
- uint8_t *bootloader_entry;
-
- bootloader_entry = memory_region_get_ram_ptr(prom);
- write_bootloader(env, bootloader_entry, entry);
- env->pc = LEON3_PROM_OFFSET;
- env->npc = LEON3_PROM_OFFSET + 4;
+ write_bootloader(memory_region_get_ram_ptr(prom), entry);
reset_info->entry = LEON3_PROM_OFFSET;
+ for (i = 0; i < machine->smp.cpus; i++) {
+ reset_info->info[i].cpu->env.pc = LEON3_PROM_OFFSET;
+ reset_info->info[i].cpu->env.npc = LEON3_PROM_OFFSET + 4;
+ }
}
}
@@ -384,6 +439,7 @@ static void leon3_generic_machine_init(MachineClass *mc)
mc->init = leon3_generic_hw_init;
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("LEON3");
mc->default_ram_id = "leon3.ram";
+ mc->max_cpus = MAX_CPUS;
}
DEFINE_MACHINE("leon3_generic", leon3_generic_machine_init)
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-21 22:29:00 +0000