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-rw-r--r--target/openrisc/cpu.c4
-rw-r--r--target/openrisc/fpu_helper.c13
-rw-r--r--target/openrisc/sys_helper.c45
-rw-r--r--target/openrisc/translate.c72
4 files changed, 81 insertions, 53 deletions
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 0ce4f796fa..61d748cfdc 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -22,6 +22,7 @@
#include "qemu/qemu-print.h"
#include "cpu.h"
#include "exec/exec-all.h"
+#include "fpu/softfloat-helpers.h"
#include "tcg/tcg.h"
static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
@@ -90,6 +91,9 @@ static void openrisc_cpu_reset_hold(Object *obj)
s->exception_index = -1;
cpu_set_fpcsr(&cpu->env, 0);
+ set_float_detect_tininess(float_tininess_before_rounding,
+ &cpu->env.fp_status);
+
#ifndef CONFIG_USER_ONLY
cpu->env.picmr = 0x00000000;
cpu->env.picsr = 0x00000000;
diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c
index f9e34fa2cc..8b81d2f62f 100644
--- a/target/openrisc/fpu_helper.c
+++ b/target/openrisc/fpu_helper.c
@@ -20,8 +20,8 @@
#include "qemu/osdep.h"
#include "cpu.h"
+#include "exec/exec-all.h"
#include "exec/helper-proto.h"
-#include "exception.h"
#include "fpu/softfloat.h"
static int ieee_ex_to_openrisc(int fexcp)
@@ -45,6 +45,15 @@ static int ieee_ex_to_openrisc(int fexcp)
return ret;
}
+static G_NORETURN
+void do_fpe(CPUOpenRISCState *env, uintptr_t pc)
+{
+ CPUState *cs = env_cpu(env);
+
+ cs->exception_index = EXCP_FPE;
+ cpu_loop_exit_restore(cs, pc);
+}
+
void HELPER(update_fpcsr)(CPUOpenRISCState *env)
{
int tmp = get_float_exception_flags(&env->fp_status);
@@ -55,7 +64,7 @@ void HELPER(update_fpcsr)(CPUOpenRISCState *env)
if (tmp) {
env->fpcsr |= tmp;
if (env->fpcsr & FPCSR_FPEE) {
- helper_exception(env, EXCP_FPE);
+ do_fpe(env, GETPC());
}
}
}
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index ec145960e3..ccdee3b8be 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -29,17 +29,37 @@
#define TO_SPR(group, number) (((group) << 11) + (number))
+static inline bool is_user(CPUOpenRISCState *env)
+{
+#ifdef CONFIG_USER_ONLY
+ return true;
+#else
+ return (env->sr & SR_SM) == 0;
+#endif
+}
+
void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
{
-#ifndef CONFIG_USER_ONLY
OpenRISCCPU *cpu = env_archcpu(env);
+#ifndef CONFIG_USER_ONLY
CPUState *cs = env_cpu(env);
target_ulong mr;
int idx;
#endif
+ /* Handle user accessible SPRs first. */
switch (spr) {
+ case TO_SPR(0, 20): /* FPCSR */
+ cpu_set_fpcsr(env, rb);
+ return;
+ }
+
+ if (is_user(env)) {
+ raise_exception(cpu, EXCP_ILLEGAL);
+ }
+
#ifndef CONFIG_USER_ONLY
+ switch (spr) {
case TO_SPR(0, 11): /* EVBAR */
env->evbar = rb;
break;
@@ -187,27 +207,33 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
cpu_openrisc_timer_update(cpu);
qemu_mutex_unlock_iothread();
break;
-#endif
-
- case TO_SPR(0, 20): /* FPCSR */
- cpu_set_fpcsr(env, rb);
- break;
}
+#endif
}
target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
target_ulong spr)
{
+ OpenRISCCPU *cpu = env_archcpu(env);
#ifndef CONFIG_USER_ONLY
uint64_t data[TARGET_INSN_START_WORDS];
MachineState *ms = MACHINE(qdev_get_machine());
- OpenRISCCPU *cpu = env_archcpu(env);
CPUState *cs = env_cpu(env);
int idx;
#endif
+ /* Handle user accessible SPRs first. */
switch (spr) {
+ case TO_SPR(0, 20): /* FPCSR */
+ return env->fpcsr;
+ }
+
+ if (is_user(env)) {
+ raise_exception(cpu, EXCP_ILLEGAL);
+ }
+
#ifndef CONFIG_USER_ONLY
+ switch (spr) {
case TO_SPR(0, 0): /* VR */
return env->vr;
@@ -324,11 +350,8 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
cpu_openrisc_count_update(cpu);
qemu_mutex_unlock_iothread();
return cpu_openrisc_count_get(cpu);
-#endif
-
- case TO_SPR(0, 20): /* FPCSR */
- return env->fpcsr;
}
+#endif
/* for rd is passed in, if rd unchanged, just keep it back. */
return rd;
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 76e53c78d4..43ba0cc1ad 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -819,45 +819,12 @@ static bool trans_l_xori(DisasContext *dc, arg_rri *a)
static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a)
{
- check_r0_write(dc, a->d);
-
- if (is_user(dc)) {
- gen_illegal_exception(dc);
- } else {
- TCGv spr = tcg_temp_new();
-
- if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- if (dc->delayed_branch) {
- tcg_gen_mov_tl(cpu_pc, jmp_pc);
- tcg_gen_discard_tl(jmp_pc);
- } else {
- tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4);
- }
- dc->base.is_jmp = DISAS_EXIT;
- }
+ TCGv spr = tcg_temp_new();
- tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k);
- gen_helper_mfspr(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d), spr);
- }
- return true;
-}
-
-static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a)
-{
- if (is_user(dc)) {
- gen_illegal_exception(dc);
- } else {
- TCGv spr;
+ check_r0_write(dc, a->d);
- if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- /* For SR, we will need to exit the TB to recognize the new
- * exception state. For NPC, in theory this counts as a branch
- * (although the SPR only exists for use by an ICE). Save all
- * of the cpu state first, allowing it to be overwritten.
- */
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
if (dc->delayed_branch) {
tcg_gen_mov_tl(cpu_pc, jmp_pc);
tcg_gen_discard_tl(jmp_pc);
@@ -865,11 +832,36 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a)
tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4);
}
dc->base.is_jmp = DISAS_EXIT;
+ }
+
+ tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k);
+ gen_helper_mfspr(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d), spr);
+ return true;
+}
+
+static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a)
+{
+ TCGv spr = tcg_temp_new();
- spr = tcg_temp_new();
- tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k);
- gen_helper_mtspr(cpu_env, spr, cpu_R(dc, a->b));
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
}
+ /*
+ * For SR, we will need to exit the TB to recognize the new
+ * exception state. For NPC, in theory this counts as a branch
+ * (although the SPR only exists for use by an ICE). Save all
+ * of the cpu state first, allowing it to be overwritten.
+ */
+ if (dc->delayed_branch) {
+ tcg_gen_mov_tl(cpu_pc, jmp_pc);
+ tcg_gen_discard_tl(jmp_pc);
+ } else {
+ tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4);
+ }
+ dc->base.is_jmp = DISAS_EXIT;
+
+ tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k);
+ gen_helper_mtspr(cpu_env, spr, cpu_R(dc, a->b));
return true;
}
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-21 07:57:39 +0000