diff options
| -rw-r--r-- | target-m68k/cpu.c | 2 | ||||
| -rw-r--r-- | target-m68k/cpu.h | 46 | ||||
| -rw-r--r-- | target-m68k/helper.c | 359 | ||||
| -rw-r--r-- | target-m68k/helper.h | 6 | ||||
| -rw-r--r-- | target-m68k/op_helper.c | 30 | ||||
| -rw-r--r-- | target-m68k/qregs.def | 6 | ||||
| -rw-r--r-- | target-m68k/translate.c | 407 |
7 files changed, 359 insertions, 497 deletions
diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c index ef02d9f60e..ba17480098 100644 --- a/target-m68k/cpu.c +++ b/target-m68k/cpu.c @@ -58,7 +58,7 @@ static void m68k_cpu_reset(CPUState *s) #endif m68k_switch_sp(env); /* ??? FP regs should be initialized to NaN. */ - env->cc_op = CC_OP_FLAGS; + cpu_m68k_set_ccr(env, 0); /* TODO: We should set PC from the interrupt vector. */ env->pc = 0; tlb_flush(s, 1); diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h index c0de97826d..48c5b811f3 100644 --- a/target-m68k/cpu.h +++ b/target-m68k/cpu.h @@ -75,9 +75,11 @@ typedef struct CPUM68KState { /* Condition flags. */ uint32_t cc_op; - uint32_t cc_dest; - uint32_t cc_src; - uint32_t cc_x; + uint32_t cc_x; /* always 0/1 */ + uint32_t cc_n; /* in bit 31 (i.e. negative) */ + uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */ + uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */ + uint32_t cc_z; /* == 0 or unused */ float64 fregs[8]; float64 fp_result; @@ -170,27 +172,23 @@ void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); * are only needed for conditional branches. */ typedef enum { - CC_OP_DYNAMIC, /* Use env->cc_op */ - CC_OP_FLAGS, /* CC_DEST = CVZN, CC_SRC = unused */ - CC_OP_LOGICB, /* CC_DEST = result, CC_SRC = unused */ - CC_OP_LOGICW, /* CC_DEST = result, CC_SRC = unused */ - CC_OP_LOGIC, /* CC_DEST = result, CC_SRC = unused */ - CC_OP_ADDB, /* CC_DEST = result, CC_SRC = source */ - CC_OP_ADDW, /* CC_DEST = result, CC_SRC = source */ - CC_OP_ADD, /* CC_DEST = result, CC_SRC = source */ - CC_OP_SUBB, /* CC_DEST = result, CC_SRC = source */ - CC_OP_SUBW, /* CC_DEST = result, CC_SRC = source */ - CC_OP_SUB, /* CC_DEST = result, CC_SRC = source */ - CC_OP_ADDXB, /* CC_DEST = result, CC_SRC = source */ - CC_OP_ADDXW, /* CC_DEST = result, CC_SRC = source */ - CC_OP_ADDX, /* CC_DEST = result, CC_SRC = source */ - CC_OP_SUBXB, /* CC_DEST = result, CC_SRC = source */ - CC_OP_SUBXW, /* CC_DEST = result, CC_SRC = source */ - CC_OP_SUBX, /* CC_DEST = result, CC_SRC = source */ - CC_OP_SHIFTB, /* CC_DEST = result, CC_SRC = carry */ - CC_OP_SHIFTW, /* CC_DEST = result, CC_SRC = carry */ - CC_OP_SHIFT, /* CC_DEST = result, CC_SRC = carry */ - CC_OP_NB, + /* Translator only -- use env->cc_op. */ + CC_OP_DYNAMIC = -1, + + /* Each flag bit computed into cc_[xcnvz]. */ + CC_OP_FLAGS, + + /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v. */ + CC_OP_ADD, + CC_OP_SUB, + + /* X in cc_x, {N,Z,C,V} via cc_n/cc_v. */ + CC_OP_CMP, + + /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n. */ + CC_OP_LOGIC, + + CC_OP_NB } CCOp; #define CCF_C 0x01 diff --git a/target-m68k/helper.c b/target-m68k/helper.c index a9974b1b73..094a7e59a9 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -132,151 +132,6 @@ void m68k_cpu_init_gdb(M68kCPU *cpu) /* TODO: Add [E]MAC registers. */ } -static uint32_t cpu_m68k_flush_flags(CPUM68KState *env, int op) -{ - int flags; - uint32_t src; - uint32_t dest; - uint32_t tmp; - -#define HIGHBIT(type) (1u << (sizeof(type) * 8 - 1)) - -#define SET_NZ(x, type) do { \ - if ((type)(x) == 0) { \ - flags |= CCF_Z; \ - } else if ((type)(x) < 0) { \ - flags |= CCF_N; \ - } \ - } while (0) - -#define SET_FLAGS_SUB(type, utype) do { \ - SET_NZ(dest, type); \ - tmp = dest + src; \ - if ((utype) tmp < (utype) src) { \ - flags |= CCF_C; \ - } \ - if (HIGHBIT(type) & (tmp ^ dest) & (tmp ^ src)) { \ - flags |= CCF_V; \ - } \ - } while (0) - -#define SET_FLAGS_ADD(type, utype) do { \ - SET_NZ(dest, type); \ - if ((utype) dest < (utype) src) { \ - flags |= CCF_C; \ - } \ - tmp = dest - src; \ - if (HIGHBIT(type) & (src ^ dest) & ~(tmp ^ src)) { \ - flags |= CCF_V; \ - } \ - } while (0) - -#define SET_FLAGS_ADDX(type, utype) do { \ - SET_NZ(dest, type); \ - if ((utype) dest <= (utype) src) { \ - flags |= CCF_C; \ - } \ - tmp = dest - src - 1; \ - if (HIGHBIT(type) & (src ^ dest) & ~(tmp ^ src)) { \ - flags |= CCF_V; \ - } \ - } while (0) - -#define SET_FLAGS_SUBX(type, utype) do { \ - SET_NZ(dest, type); \ - tmp = dest + src + 1; \ - if ((utype) tmp <= (utype) src) { \ - flags |= CCF_C; \ - } \ - if (HIGHBIT(type) & (tmp ^ dest) & (tmp ^ src)) { \ - flags |= CCF_V; \ - } \ - } while (0) - -#define SET_FLAGS_SHIFT(type) do { \ - SET_NZ(dest, type); \ - flags |= src; \ - } while (0) - - flags = 0; - src = env->cc_src; - dest = env->cc_dest; - switch (op) { - case CC_OP_FLAGS: - flags = dest; - break; - case CC_OP_LOGICB: - SET_NZ(dest, int8_t); - break; - case CC_OP_LOGICW: - SET_NZ(dest, int16_t); - break; - case CC_OP_LOGIC: - SET_NZ(dest, int32_t); - break; - case CC_OP_ADDB: - SET_FLAGS_ADD(int8_t, uint8_t); - break; - case CC_OP_ADDW: - SET_FLAGS_ADD(int16_t, uint16_t); - break; - case CC_OP_ADD: - SET_FLAGS_ADD(int32_t, uint32_t); - break; - case CC_OP_SUBB: - SET_FLAGS_SUB(int8_t, uint8_t); - break; - case CC_OP_SUBW: - SET_FLAGS_SUB(int16_t, uint16_t); - break; - case CC_OP_SUB: - SET_FLAGS_SUB(int32_t, uint32_t); - break; - case CC_OP_ADDXB: - SET_FLAGS_ADDX(int8_t, uint8_t); - break; - case CC_OP_ADDXW: - SET_FLAGS_ADDX(int16_t, uint16_t); - break; - case CC_OP_ADDX: - SET_FLAGS_ADDX(int32_t, uint32_t); - break; - case CC_OP_SUBXB: - SET_FLAGS_SUBX(int8_t, uint8_t); - break; - case CC_OP_SUBXW: - SET_FLAGS_SUBX(int16_t, uint16_t); - break; - case CC_OP_SUBX: - SET_FLAGS_SUBX(int32_t, uint32_t); - break; - case CC_OP_SHIFTB: - SET_FLAGS_SHIFT(int8_t); - break; - case CC_OP_SHIFTW: - SET_FLAGS_SHIFT(int16_t); - break; - case CC_OP_SHIFT: - SET_FLAGS_SHIFT(int32_t); - break; - default: - g_assert_not_reached(); - } - return flags; -} - -uint32_t cpu_m68k_get_ccr(CPUM68KState *env) -{ - return cpu_m68k_flush_flags(env, env->cc_op) | env->cc_x * CCF_X; -} - -void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t val) -{ - env->cc_op = CC_OP_FLAGS; - env->cc_dest = val & 0xf; - env->cc_x = (val & CCF_X ? 1 : 0); -} - void HELPER(movec)(CPUM68KState *env, uint32_t reg, uint32_t val) { M68kCPU *cpu = m68k_env_get_cpu(env); @@ -413,59 +268,52 @@ uint32_t HELPER(ff1)(uint32_t x) return n; } -uint32_t HELPER(sats)(uint32_t val, uint32_t ccr) +uint32_t HELPER(sats)(uint32_t val, uint32_t v) { /* The result has the opposite sign to the original value. */ - if (ccr & CCF_V) + if ((int32_t)v < 0) { val = (((int32_t)val) >> 31) ^ SIGNBIT; + } return val; } uint32_t HELPER(subx_cc)(CPUM68KState *env, uint32_t op1, uint32_t op2) { - uint32_t res; - uint32_t old_flags; - int op; + uint32_t res, new_x; - old_flags = env->cc_dest; if (env->cc_x) { - env->cc_x = (op1 <= op2); - op = CC_OP_SUBX; + new_x = (op1 <= op2); res = op1 - (op2 + 1); } else { - env->cc_x = (op1 < op2); - op = CC_OP_SUB; + new_x = (op1 < op2); res = op1 - op2; } - env->cc_dest = res; - env->cc_src = op2; - env->cc_dest = cpu_m68k_flush_flags(env, op); - /* !Z is sticky. */ - env->cc_dest &= (old_flags | ~CCF_Z); + env->cc_x = new_x; + env->cc_c = new_x; + env->cc_n = res; + env->cc_z |= res; /* !Z is sticky */ + env->cc_v = (res ^ op1) & (op1 ^ op2); + return res; } uint32_t HELPER(addx_cc)(CPUM68KState *env, uint32_t op1, uint32_t op2) { - uint32_t res; - uint32_t old_flags; - int op; + uint32_t res, new_x; - old_flags = env->cc_dest; if (env->cc_x) { res = op1 + op2 + 1; - env->cc_x = (res <= op2); - op = CC_OP_ADDX; + new_x = (res <= op2); } else { res = op1 + op2; - env->cc_x = (res < op2); - op = CC_OP_ADD; + new_x = (res < op2); } - env->cc_dest = res; - env->cc_src = op2; - env->cc_dest = cpu_m68k_flush_flags(env, op); - /* !Z is sticky. */ - env->cc_dest &= (old_flags | ~CCF_Z); + env->cc_x = new_x; + env->cc_c = new_x; + env->cc_n = res; + env->cc_z |= res; /* !Z is sticky. */ + env->cc_v = (res ^ op1) & ~(op1 ^ op2); + return res; } @@ -478,73 +326,53 @@ void HELPER(set_sr)(CPUM68KState *env, uint32_t val) uint32_t HELPER(shl_cc)(CPUM68KState *env, uint32_t val, uint32_t shift) { - uint32_t result; - uint32_t cf; + uint64_t result; shift &= 63; - if (shift == 0) { - result = val; - cf = env->cc_src & CCF_C; - } else if (shift < 32) { - result = val << shift; - cf = (val >> (32 - shift)) & 1; - } else if (shift == 32) { - result = 0; - cf = val & 1; - } else /* shift > 32 */ { - result = 0; - cf = 0; - } - env->cc_src = cf; - env->cc_x = (cf != 0); - env->cc_dest = result; + result = (uint64_t)val << shift; + + env->cc_c = (result >> 32) & 1; + env->cc_n = result; + env->cc_z = result; + env->cc_v = 0; + env->cc_x = shift ? env->cc_c : env->cc_x; + return result; } uint32_t HELPER(shr_cc)(CPUM68KState *env, uint32_t val, uint32_t shift) { + uint64_t temp; uint32_t result; - uint32_t cf; shift &= 63; - if (shift == 0) { - result = val; - cf = env->cc_src & CCF_C; - } else if (shift < 32) { - result = val >> shift; - cf = (val >> (shift - 1)) & 1; - } else if (shift == 32) { - result = 0; - cf = val >> 31; - } else /* shift > 32 */ { - result = 0; - cf = 0; - } - env->cc_src = cf; - env->cc_x = (cf != 0); - env->cc_dest = result; + temp = (uint64_t)val << 32 >> shift; + result = temp >> 32; + + env->cc_c = (temp >> 31) & 1; + env->cc_n = result; + env->cc_z = result; + env->cc_v = 0; + env->cc_x = shift ? env->cc_c : env->cc_x; + return result; } uint32_t HELPER(sar_cc)(CPUM68KState *env, uint32_t val, uint32_t shift) { + uint64_t temp; uint32_t result; - uint32_t cf; shift &= 63; - if (shift == 0) { - result = val; - cf = (env->cc_src & CCF_C) != 0; - } else if (shift < 32) { - result = (int32_t)val >> shift; - cf = (val >> (shift - 1)) & 1; - } else /* shift >= 32 */ { - result = (int32_t)val >> 31; - cf = val >> 31; - } - env->cc_src = cf; - env->cc_x = cf; - env->cc_dest = result; + temp = (int64_t)val << 32 >> shift; + result = temp >> 32; + + env->cc_c = (temp >> 31) & 1; + env->cc_n = result; + env->cc_z = result; + env->cc_v = result ^ val; + env->cc_x = shift ? env->cc_c : env->cc_x; + return result; } @@ -796,9 +624,92 @@ void HELPER(mac_set_flags)(CPUM68KState *env, uint32_t acc) } } -uint32_t HELPER(flush_flags)(CPUM68KState *env, uint32_t op) + +#define COMPUTE_CCR(op, x, n, z, v, c) { \ + switch (op) { \ + case CC_OP_FLAGS: \ + /* Everything in place. */ \ + break; \ + case CC_OP_ADD: \ + res = n; \ + src2 = v; \ + src1 = res - src2; \ + c = x; \ + z = n; \ + v = (res ^ src1) & ~(src1 ^ src2); \ + break; \ + case CC_OP_SUB: \ + res = n; \ + src2 = v; \ + src1 = res + src2; \ + c = x; \ + z = n; \ + v = (res ^ src1) & (src1 ^ src2); \ + break; \ + case CC_OP_CMP: \ + src1 = n; \ + src2 = v; \ + res = src1 - src2; \ + n = res; \ + z = res; \ + c = src1 < src2; \ + v = (res ^ src1) & (src1 ^ src2); \ + break; \ + case CC_OP_LOGIC: \ + c = v = 0; \ + z = n; \ + break; \ + default: \ + cpu_abort(CPU(m68k_env_get_cpu(env)), "Bad CC_OP %d", op); \ + } \ +} while (0) + +uint32_t cpu_m68k_get_ccr(CPUM68KState *env) { - return cpu_m68k_flush_flags(env, op); + uint32_t x, c, n, z, v; + uint32_t res, src1, src2; + + x = env->cc_x; + c = env->cc_c; + n = env->cc_n; + z = env->cc_z; + v = env->cc_v; + + COMPUTE_CCR(env->cc_op, x, n, z, v, c); + + n = n >> 31; + v = v >> 31; + z = (z == 0); + + return x * CCF_X + n * CCF_N + z * CCF_Z + v * CCF_V + c * CCF_C; +} + +uint32_t HELPER(get_ccr)(CPUM68KState *env) +{ + return cpu_m68k_get_ccr(env); +} + +void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t ccr) +{ + env->cc_x = (ccr & CCF_X ? 1 : 0); + env->cc_n = (ccr & CCF_N ? -1 : 0); + env->cc_z = (ccr & CCF_Z ? 0 : 1); + env->cc_v = (ccr & CCF_V ? -1 : 0); + env->cc_c = (ccr & CCF_C ? 1 : 0); + env->cc_op = CC_OP_FLAGS; +} + +void HELPER(set_ccr)(CPUM68KState *env, uint32_t ccr) +{ + cpu_m68k_set_ccr(env, ccr); +} + +void HELPER(flush_flags)(CPUM68KState *env, uint32_t cc_op) +{ + uint32_t res, src1, src2; + + COMPUTE_CCR(cc_op, env->cc_x, env->cc_n, env->cc_z, env->cc_v, env->cc_c); + env->cc_op = CC_OP_FLAGS; } uint32_t HELPER(get_macf)(CPUM68KState *env, uint64_t val) diff --git a/target-m68k/helper.h b/target-m68k/helper.h index 0f5a7cf799..c8681480f0 100644 --- a/target-m68k/helper.h +++ b/target-m68k/helper.h @@ -1,6 +1,6 @@ DEF_HELPER_1(bitrev, i32, i32) DEF_HELPER_1(ff1, i32, i32) -DEF_HELPER_2(sats, i32, i32, i32) +DEF_HELPER_FLAGS_2(sats, TCG_CALL_NO_RWG_SE, i32, i32, i32) DEF_HELPER_2(divu, void, env, i32) DEF_HELPER_2(divs, void, env, i32) DEF_HELPER_3(addx_cc, i32, env, i32, i32) @@ -45,5 +45,7 @@ DEF_HELPER_3(set_mac_extf, void, env, i32, i32) DEF_HELPER_3(set_mac_exts, void, env, i32, i32) DEF_HELPER_3(set_mac_extu, void, env, i32, i32) -DEF_HELPER_2(flush_flags, i32, env, i32) +DEF_HELPER_2(flush_flags, void, env, i32) +DEF_HELPER_2(set_ccr, void, env, i32) +DEF_HELPER_FLAGS_1(get_ccr, TCG_CALL_NO_WG_SE, i32, env) DEF_HELPER_2(raise_exception, void, env, i32) diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c index af361776a6..48e02e4062 100644 --- a/target-m68k/op_helper.c +++ b/target-m68k/op_helper.c @@ -185,7 +185,6 @@ void HELPER(divu)(CPUM68KState *env, uint32_t word) uint32_t den; uint32_t quot; uint32_t rem; - uint32_t flags; num = env->div1; den = env->div2; @@ -195,16 +194,14 @@ void HELPER(divu)(CPUM68KState *env, uint32_t word) } quot = num / den; rem = num % den; - flags = 0; - if (word && quot > 0xffff) - flags |= CCF_V; - if (quot == 0) - flags |= CCF_Z; - else if ((int32_t)quot < 0) - flags |= CCF_N; + + env->cc_v = (word && quot > 0xffff ? -1 : 0); + env->cc_z = quot; + env->cc_n = quot; + env->cc_c = 0; + env->div1 = quot; env->div2 = rem; - env->cc_dest = flags; } void HELPER(divs)(CPUM68KState *env, uint32_t word) @@ -213,7 +210,6 @@ void HELPER(divs)(CPUM68KState *env, uint32_t word) int32_t den; int32_t quot; int32_t rem; - int32_t flags; num = env->div1; den = env->div2; @@ -222,14 +218,12 @@ void HELPER(divs)(CPUM68KState *env, uint32_t word) } quot = num / den; rem = num % den; - flags = 0; - if (word && quot != (int16_t)quot) - flags |= CCF_V; - if (quot == 0) - flags |= CCF_Z; - else if (quot < 0) - flags |= CCF_N; + + env->cc_v = (word && quot != (int16_t)quot ? -1 : 0); + env->cc_z = quot; + env->cc_n = quot; + env->cc_c = 0; + env->div1 = quot; env->div2 = rem; - env->cc_dest = flags; } diff --git a/target-m68k/qregs.def b/target-m68k/qregs.def index 204663e1aa..156c0f558f 100644 --- a/target-m68k/qregs.def +++ b/target-m68k/qregs.def @@ -2,9 +2,11 @@ DEFF64(FP_RESULT, fp_result) DEFO32(PC, pc) DEFO32(SR, sr) DEFO32(CC_OP, cc_op) -DEFO32(CC_DEST, cc_dest) -DEFO32(CC_SRC, cc_src) DEFO32(CC_X, cc_x) +DEFO32(CC_C, cc_c) +DEFO32(CC_N, cc_n) +DEFO32(CC_V, cc_v) +DEFO32(CC_Z, cc_z) DEFO32(DIV1, div1) DEFO32(DIV2, div2) DEFO32(MACSR, macsr) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 73f9e9f483..85d5c95bc3 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -134,6 +134,7 @@ typedef struct DisasContext { target_ulong pc; int is_jmp; CCOp cc_op; /* Current CC operation */ + int cc_op_synced; int user; uint32_t fpcr; struct TranslationBlock *tb; @@ -175,49 +176,44 @@ typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn); uint16_t insn) #endif -enum { - USES_CC_DST = 1, - USES_CC_SRC = 2, -}; - static const uint8_t cc_op_live[CC_OP_NB] = { - [CC_OP_DYNAMIC] = USES_CC_DST | USES_CC_SRC, - [CC_OP_FLAGS] = USES_CC_DST, - [CC_OP_LOGICB ... CC_OP_LOGIC] = USES_CC_DST, - [CC_OP_ADDB ... CC_OP_ADD] = USES_CC_DST | USES_CC_SRC, - [CC_OP_SUBB ... CC_OP_SUB] = USES_CC_DST | USES_CC_SRC, - [CC_OP_ADDXB ... CC_OP_ADDX] = USES_CC_DST | USES_CC_SRC, - [CC_OP_SUBXB ... CC_OP_SUBX] = USES_CC_DST | USES_CC_SRC, - [CC_OP_SHIFTB ... CC_OP_SHIFT] = USES_CC_DST | USES_CC_SRC, + [CC_OP_FLAGS] = CCF_C | CCF_V | CCF_Z | CCF_N | CCF_X, + [CC_OP_ADD] = CCF_X | CCF_N | CCF_V, + [CC_OP_SUB] = CCF_X | CCF_N | CCF_V, + [CC_OP_CMP] = CCF_X | CCF_N | CCF_V, + [CC_OP_LOGIC] = CCF_X | CCF_N }; static void set_cc_op(DisasContext *s, CCOp op) { + CCOp old_op = s->cc_op; int dead; - if (s->cc_op == op) { + if (old_op == op) { return; } + s->cc_op = op; + s->cc_op_synced = 0; - /* Discard CC computation that will no longer be used. */ - - dead = cc_op_live[s->cc_op] & ~cc_op_live[op]; - if (dead & USES_CC_DST) { - tcg_gen_discard_i32(QREG_CC_DEST); + /* Discard CC computation that will no longer be used. + Note that X and N are never dead. */ + dead = cc_op_live[old_op] & ~cc_op_live[op]; + if (dead & CCF_C) { + tcg_gen_discard_i32(QREG_CC_C); } - if (dead & USES_CC_SRC) { - tcg_gen_discard_i32(QREG_CC_SRC); + if (dead & CCF_Z) { + tcg_gen_discard_i32(QREG_CC_Z); } - if (s->cc_op == CC_OP_DYNAMIC) { - tcg_gen_discard_i32(QREG_CC_OP); + if (dead & CCF_V) { + tcg_gen_discard_i32(QREG_CC_V); } - s->cc_op = op; } /* Update the CPU env CC_OP state. */ -static inline void update_cc_op(DisasContext *s) +static void update_cc_op(DisasContext *s) { - if (s->cc_op != CC_OP_DYNAMIC) { + if (!s->cc_op_synced) { + s->cc_op_synced = 1; tcg_gen_movi_i32(QREG_CC_OP, s->cc_op); } } @@ -460,41 +456,79 @@ static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base) /* Evaluate all the CC flags. */ -static inline void gen_flush_flags(DisasContext *s) +static void gen_flush_flags(DisasContext *s) { - if (s->cc_op == CC_OP_FLAGS) + TCGv tmp; + + switch (s->cc_op) { + case CC_OP_FLAGS: return; - if (s->cc_op == CC_OP_DYNAMIC) { - gen_helper_flush_flags(QREG_CC_DEST, cpu_env, QREG_CC_OP); - } else { - gen_helper_flush_flags(QREG_CC_DEST, cpu_env, tcg_const_i32(s->cc_op)); + case CC_OP_DYNAMIC: + gen_helper_flush_flags(cpu_env, QREG_CC_OP); + break; + default: + tmp = tcg_const_i32(s->cc_op); + gen_helper_flush_flags(cpu_env, tmp); + tcg_temp_free(tmp); + break; + } + + /* Note that flush_flags also assigned to env->cc_op. */ + s->cc_op = CC_OP_FLAGS; + s->cc_op_synced = 1; +} + +/* Sign or zero extend a value. */ + +static inline void gen_ext(TCGv res, TCGv val, int opsize, int sign) +{ + switch (opsize) { + case OS_BYTE: + if (sign) { + tcg_gen_ext8s_i32(res, val); + } else { + tcg_gen_ext8u_i32(res, val); + } + break; + case OS_WORD: + if (sign) { + tcg_gen_ext16s_i32(res, val); + } else { + tcg_gen_ext16u_i32(res, val); + } + break; + case OS_LONG: + tcg_gen_mov_i32(res, val); + break; + default: + g_assert_not_reached(); } - set_cc_op(s, CC_OP_FLAGS); } -#define SET_CC_OP(opsize, op) do { \ - switch (opsize) { \ - case OS_BYTE: \ - set_cc_op(s, CC_OP_##op##B); break; \ - case OS_WORD: \ - set_cc_op(s, CC_OP_##op##W); break; \ - case OS_LONG: \ - set_cc_op(s, CC_OP_##op); break; \ - default: \ - abort(); \ - } \ -} while (0) +static TCGv gen_extend(TCGv val, int opsize, int sign) +{ + TCGv tmp; + + if (opsize == OS_LONG) { + tmp = val; + } else { + tmp = tcg_temp_new(); + gen_ext(tmp, val, opsize, sign); + } + + return tmp; +} static void gen_logic_cc(DisasContext *s, TCGv val, int opsize) { - tcg_gen_mov_i32(QREG_CC_DEST, val); - SET_CC_OP(opsize, LOGIC); + gen_ext(QREG_CC_N, val, opsize, 1); + set_cc_op(s, CC_OP_LOGIC); } static void gen_update_cc_add(TCGv dest, TCGv src) { - tcg_gen_mov_i32(QREG_CC_DEST, dest); - tcg_gen_mov_i32(QREG_CC_SRC, src); + tcg_gen_mov_i32(QREG_CC_N, dest); + tcg_gen_mov_i32(QREG_CC_V, src); } static inline int opsize_bytes(int opsize) @@ -550,36 +584,6 @@ static void gen_partset_reg(int opsize, TCGv reg, TCGv val) } } -/* Sign or zero extend a value. */ -static inline TCGv gen_extend(TCGv val, int opsize, int sign) -{ - TCGv tmp; - - switch (opsize) { - case OS_BYTE: - tmp = tcg_temp_new(); - if (sign) - tcg_gen_ext8s_i32(tmp, val); - else - tcg_gen_ext8u_i32(tmp, val); - break; - case OS_WORD: - tmp = tcg_temp_new(); - if (sign) - tcg_gen_ext16s_i32(tmp, val); - else - tcg_gen_ext16u_i32(tmp, val); - break; - case OS_LONG: - case OS_SINGLE: - tmp = val; - break; - default: - g_assert_not_reached(); - } - return tmp; -} - /* Generate code for an "effective address". Does not adjust the base register for autoincrement addressing modes. */ static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn, @@ -758,7 +762,8 @@ static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn, /* This generates a conditional branch, clobbering all temporaries. */ static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1) { - TCGv tmp; + TCGv tmp, tmp2; + TCGCond tcond; /* TODO: Optimize compare/branch pairs rather than always flushing flag state to CC_OP_FLAGS. */ @@ -767,97 +772,57 @@ static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1) switch (cond) { case 0: /* T */ tcg_gen_br(l1); - break; + return; case 1: /* F */ - break; - case 2: /* HI (!C && !Z) */ - tmp = tcg_temp_new(); - tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z); - tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); - break; + return; + case 2: /* HI (!C && !Z) -> !(C || Z)*/ case 3: /* LS (C || Z) */ tmp = tcg_temp_new(); - tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z); - tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); + tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, QREG_CC_Z, 0); + tcg_gen_or_i32(tmp, tmp, QREG_CC_C); + tcond = (cond & 1 ? TCG_COND_NE : TCG_COND_EQ); break; case 4: /* CC (!C) */ - tmp = tcg_temp_new(); - tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C); - tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); - break; case 5: /* CS (C) */ - tmp = tcg_temp_new(); - tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C); - tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); + tmp = QREG_CC_C; + tcond = (cond & 1 ? TCG_COND_NE : TCG_COND_EQ); break; case 6: /* NE (!Z) */ - tmp = tcg_temp_new(); - tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z); - tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); - break; case 7: /* EQ (Z) */ - tmp = tcg_temp_new(); - tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z); - tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); + tmp = QREG_CC_Z; + tcond = (cond & 1 ? TCG_COND_EQ : TCG_COND_NE); break; case 8: /* VC (!V) */ - tmp = tcg_temp_new(); - tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V); - tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); - break; case 9: /* VS (V) */ - tmp = tcg_temp_new(); - tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V); - tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); + tmp = QREG_CC_V; + tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE); break; case 10: /* PL (!N) */ - tmp = tcg_temp_new(); - tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N); - tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); - break; case 11: /* MI (N) */ - tmp = tcg_temp_new(); - tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N); - tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); + tmp = QREG_CC_N; + tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE); break; case 12: /* GE (!(N ^ V)) */ - tmp = tcg_temp_new(); - assert(CCF_V == (CCF_N >> 2)); - tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2); - tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST); - tcg_gen_andi_i32(tmp, tmp, CCF_V); - tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); - break; case 13: /* LT (N ^ V) */ tmp = tcg_temp_new(); - assert(CCF_V == (CCF_N >> 2)); - tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2); - tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST); - tcg_gen_andi_i32(tmp, tmp, CCF_V); - tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); + tcg_gen_xor_i32(tmp, QREG_CC_N, QREG_CC_V); + tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE); break; case 14: /* GT (!(Z || (N ^ V))) */ - tmp = tcg_temp_new(); - assert(CCF_V == (CCF_N >> 2)); - tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N); - tcg_gen_shri_i32(tmp, tmp, 2); - tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST); - tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z); - tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1); - break; case 15: /* LE (Z || (N ^ V)) */ tmp = tcg_temp_new(); - assert(CCF_V == (CCF_N >> 2)); - tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N); - tcg_gen_shri_i32(tmp, tmp, 2); - tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST); - tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z); - tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1); + tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, QREG_CC_Z, 0); + tcg_gen_neg_i32(tmp, tmp); + tmp2 = tcg_temp_new(); + tcg_gen_xor_i32(tmp2, QREG_CC_N, QREG_CC_V); + tcg_gen_or_i32(tmp, tmp, tmp2); + tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE); break; default: /* Should ever happen. */ abort(); } + tcg_gen_brcondi_i32(tcond, tmp, 0, l1); } DISAS_INSN(scc) @@ -1021,6 +986,7 @@ DISAS_INSN(divw) tcg_gen_ext16u_i32(tmp, QREG_DIV1); tcg_gen_shli_i32(src, QREG_DIV2, 16); tcg_gen_or_i32(reg, tmp, src); + set_cc_op(s, CC_OP_FLAGS); } @@ -1116,42 +1082,43 @@ DISAS_INSN(bitop_reg) else opsize = OS_LONG; op = (insn >> 6) & 3; + + gen_flush_flags(s); + SRC_EA(env, src1, opsize, 0, op ? &addr: NULL); src2 = DREG(insn, 9); dest = tcg_temp_new(); - gen_flush_flags(s); tmp = tcg_temp_new(); if (opsize == OS_BYTE) tcg_gen_andi_i32(tmp, src2, 7); else tcg_gen_andi_i32(tmp, src2, 31); - src2 = tmp; - tmp = tcg_temp_new(); - tcg_gen_shr_i32(tmp, src1, src2); - tcg_gen_andi_i32(tmp, tmp, 1); - tcg_gen_shli_i32(tmp, tmp, 2); - /* Clear CCF_Z if bit set. */ - tcg_gen_ori_i32(QREG_CC_DEST, QREG_CC_DEST, CCF_Z); - tcg_gen_xor_i32(QREG_CC_DEST, QREG_CC_DEST, tmp); - - tcg_gen_shl_i32(tmp, tcg_const_i32(1), src2); + + src2 = tcg_const_i32(1); + tcg_gen_shl_i32(src2, src2, tmp); + tcg_temp_free(tmp); + + tcg_gen_and_i32(QREG_CC_Z, src1, src2); + switch (op) { case 1: /* bchg */ - tcg_gen_xor_i32(dest, src1, tmp); + tcg_gen_xor_i32(dest, src1, src2); break; case 2: /* bclr */ - tcg_gen_not_i32(tmp, tmp); - tcg_gen_and_i32(dest, src1, tmp); + tcg_gen_andc_i32(dest, src1, src2); break; case 3: /* bset */ - tcg_gen_or_i32(dest, src1, tmp); + tcg_gen_or_i32(dest, src1, src2); break; default: /* btst */ break; } - if (op) + tcg_temp_free(src2); + if (op) { DEST_EA(env, insn, opsize, dest, &addr); + } + tcg_temp_free(dest); } DISAS_INSN(sats) @@ -1159,7 +1126,7 @@ DISAS_INSN(sats) TCGv reg; reg = DREG(insn, 0); gen_flush_flags(s); - gen_helper_sats(reg, reg, QREG_CC_DEST); + gen_helper_sats(reg, reg, QREG_CC_V); gen_logic_cc(s, reg, OS_LONG); } @@ -1231,28 +1198,20 @@ DISAS_INSN(bitop_im) return; } + gen_flush_flags(s); + SRC_EA(env, src1, opsize, 0, op ? &addr: NULL); - gen_flush_flags(s); if (opsize == OS_BYTE) bitnum &= 7; else bitnum &= 31; mask = 1 << bitnum; - tmp = tcg_temp_new(); - assert (CCF_Z == (1 << 2)); - if (bitnum > 2) - tcg_gen_shri_i32(tmp, src1, bitnum - 2); - else if (bitnum < 2) - tcg_gen_shli_i32(tmp, src1, 2 - bitnum); - else - tcg_gen_mov_i32(tmp, src1); - tcg_gen_andi_i32(tmp, tmp, CCF_Z); - /* Clear CCF_Z if bit set. */ - tcg_gen_ori_i32(QREG_CC_DEST, QREG_CC_DEST, CCF_Z); - tcg_gen_xor_i32(QREG_CC_DEST, QREG_CC_DEST, tmp); + tcg_gen_andi_i32(QREG_CC_Z, src1, mask); + if (op) { + tmp = tcg_temp_new(); switch (op) { case 1: /* bchg */ tcg_gen_xori_i32(tmp, src1, mask); @@ -1267,8 +1226,10 @@ DISAS_INSN(bitop_im) break; } DEST_EA(env, insn, opsize, tmp, &addr); + tcg_temp_free(tmp); } } + DISAS_INSN(arith_im) { int op; @@ -1292,7 +1253,7 @@ DISAS_INSN(arith_im) break; case 2: /* subi */ tcg_gen_mov_i32(dest, src1); - tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, tcg_const_i32(im)); + tcg_gen_setcondi_i32(TCG_COND_LTU, QREG_CC_X, dest, im); tcg_gen_subi_i32(dest, dest, im); gen_update_cc_add(dest, tcg_const_i32(im)); set_cc_op(s, CC_OP_SUB); @@ -1301,7 +1262,7 @@ DISAS_INSN(arith_im) tcg_gen_mov_i32(dest, src1); tcg_gen_addi_i32(dest, dest, im); gen_update_cc_add(dest, tcg_const_i32(im)); - tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, tcg_const_i32(im)); + tcg_gen_setcondi_i32(TCG_COND_LTU, QREG_CC_X, dest, im); set_cc_op(s, CC_OP_ADD); break; case 5: /* eori */ @@ -1309,10 +1270,8 @@ DISAS_INSN(arith_im) gen_logic_cc(s, dest, OS_LONG); break; case 6: /* cmpi */ - tcg_gen_mov_i32(dest, src1); - tcg_gen_subi_i32(dest, dest, im); - gen_update_cc_add(dest, tcg_const_i32(im)); - set_cc_op(s, CC_OP_SUB); + gen_update_cc_add(src1, tcg_const_i32(im)); + set_cc_op(s, CC_OP_CMP); break; default: abort(); @@ -1404,9 +1363,9 @@ static TCGv gen_get_ccr(DisasContext *s) TCGv dest; gen_flush_flags(s); + update_cc_op(s); dest = tcg_temp_new(); - tcg_gen_shli_i32(dest, QREG_CC_X, 4); - tcg_gen_or_i32(dest, dest, QREG_CC_DEST); + gen_helper_get_ccr(dest, cpu_env); return dest; } @@ -1428,45 +1387,47 @@ DISAS_INSN(neg) tcg_gen_mov_i32(src1, reg); tcg_gen_neg_i32(reg, src1); gen_update_cc_add(reg, src1); - tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, tcg_const_i32(0), src1); + tcg_gen_setcondi_i32(TCG_COND_NE, QREG_CC_X, src1, 0); set_cc_op(s, CC_OP_SUB); } static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only) { - tcg_gen_movi_i32(QREG_CC_DEST, val & 0xf); - tcg_gen_movi_i32(QREG_CC_X, (val & 0x10) >> 4); - if (!ccr_only) { - gen_helper_set_sr(cpu_env, tcg_const_i32(val & 0xff00)); + if (ccr_only) { + tcg_gen_movi_i32(QREG_CC_C, val & CCF_C ? 1 : 0); + tcg_gen_movi_i32(QREG_CC_V, val & CCF_V ? -1 : 0); + tcg_gen_movi_i32(QREG_CC_Z, val & CCF_Z ? 0 : 1); + tcg_gen_movi_i32(QREG_CC_N, val & CCF_N ? -1 : 0); + tcg_gen_movi_i32(QREG_CC_X, val & CCF_X ? 1 : 0); + } else { + gen_helper_set_sr(cpu_env, tcg_const_i32(val)); } set_cc_op(s, CC_OP_FLAGS); } -static void gen_set_sr(DisasContext *s, TCGv val, int ccr_only) +static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn, + int ccr_only) { - TCGv tmp; - tmp = tcg_temp_new(); - tcg_gen_andi_i32(QREG_CC_DEST, val, 0xf); - tcg_gen_shri_i32(tmp, val, 4); - tcg_gen_andi_i32(QREG_CC_X, tmp, 1); - if (!ccr_only) { - gen_helper_set_sr(cpu_env, val); + if ((insn & 0x38) == 0) { + if (ccr_only) { + gen_helper_set_ccr(cpu_env, DREG(insn, 0)); + } else { + gen_helper_set_sr(cpu_env, DREG(insn, 0)); + } + set_cc_op(s, CC_OP_FLAGS); + } else if ((insn & 0x3f) == 0x3c) { + uint16_t val; + val = read_im16(env, s); + gen_set_sr_im(s, val, ccr_only); + } else { + disas_undef(env, s, insn); } } -static void gen_move_to_sr(CPUM68KState *env, DisasContext *s, uint16_t insn, - int ccr_only) -{ - TCGv src; - s->cc_op = CC_OP_FLAGS; - SRC_EA(env, src, OS_WORD, 0, NULL); - gen_set_sr(s, src, ccr_only); -} - DISAS_INSN(move_to_ccr) { - gen_move_to_sr(env, s, insn, 1); + gen_set_sr(env, s, insn, 1); } DISAS_INSN(not) @@ -1670,10 +1631,10 @@ DISAS_INSN(addsubq) src2 = tcg_const_i32(val); if (insn & 0x0100) { tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src2); - tcg_gen_subi_i32(dest, dest, val); + tcg_gen_sub_i32(dest, dest, src2); set_cc_op(s, CC_OP_SUB); } else { - tcg_gen_addi_i32(dest, dest, val); + tcg_gen_add_i32(dest, dest, src2); tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src2); set_cc_op(s, CC_OP_ADD); } @@ -1717,18 +1678,16 @@ DISAS_INSN(branch) /* bsr */ gen_push(s, tcg_const_i32(s->pc)); } + update_cc_op(s); if (op > 1) { /* Bcc */ l1 = gen_new_label(); gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1); - update_cc_op(s); gen_jmp_tb(s, 1, base + offset); gen_set_label(l1); - update_cc_op(s); gen_jmp_tb(s, 0, s->pc); } else { /* Unconditional branch. */ - update_cc_op(s); gen_jmp_tb(s, 0, base + offset); } } @@ -1817,16 +1776,13 @@ DISAS_INSN(cmp) { TCGv src; TCGv reg; - TCGv dest; int opsize; opsize = insn_opsize(insn); SRC_EA(env, src, opsize, -1, NULL); reg = DREG(insn, 9); - dest = tcg_temp_new(); - tcg_gen_sub_i32(dest, reg, src); - gen_update_cc_add(dest, src); - SET_CC_OP(opsize, SUB); + gen_update_cc_add(reg, src); + set_cc_op(s, CC_OP_CMP); } DISAS_INSN(cmpa) @@ -1834,7 +1790,6 @@ DISAS_INSN(cmpa) int opsize; TCGv src; TCGv reg; - TCGv dest; if (insn & 0x100) { opsize = OS_LONG; @@ -1843,10 +1798,8 @@ DISAS_INSN(cmpa) } SRC_EA(env, src, opsize, 1, NULL); reg = AREG(insn, 9); - dest = tcg_temp_new(); - tcg_gen_sub_i32(dest, reg, src); - gen_update_cc_add(dest, src); - SET_CC_OP(OS_LONG, SUB); + gen_update_cc_add(reg, src); + set_cc_op(s, CC_OP_CMP); } DISAS_INSN(eor) @@ -1913,6 +1866,8 @@ DISAS_INSN(shift_im) int tmp; TCGv shift; + set_cc_op(s, CC_OP_FLAGS); + reg = DREG(insn, 0); tmp = (insn >> 9) & 7; if (tmp == 0) @@ -1928,7 +1883,6 @@ DISAS_INSN(shift_im) gen_helper_sar_cc(reg, cpu_env, reg, shift); } } - set_cc_op(s, CC_OP_SHIFT); } DISAS_INSN(shift_reg) @@ -1938,8 +1892,6 @@ DISAS_INSN(shift_reg) reg = DREG(insn, 0); shift = DREG(insn, 9); - /* Shift by zero leaves C flag unmodified. */ - gen_flush_flags(s); if (insn & 0x100) { gen_helper_shl_cc(reg, cpu_env, reg, shift); } else { @@ -1949,7 +1901,7 @@ DISAS_INSN(shift_reg) gen_helper_sar_cc(reg, cpu_env, reg, shift); } } - set_cc_op(s, CC_OP_SHIFT); + set_cc_op(s, CC_OP_FLAGS); } DISAS_INSN(ff1) @@ -2010,7 +1962,7 @@ DISAS_INSN(move_to_sr) gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); return; } - gen_move_to_sr(env, s, insn, 0); + gen_set_sr(env, s, insn, 0); gen_lookup_tb(s); } @@ -2759,8 +2711,10 @@ DISAS_INSN(from_mext) DISAS_INSN(macsr_to_ccr) { - tcg_gen_movi_i32(QREG_CC_X, 0); - tcg_gen_andi_i32(QREG_CC_DEST, QREG_MACSR, 0xf); + TCGv tmp = tcg_temp_new(); + tcg_gen_andi_i32(tmp, QREG_MACSR, 0xf); + gen_helper_set_sr(cpu_env, tmp); + tcg_temp_free(tmp); set_cc_op(s, CC_OP_FLAGS); } @@ -3044,6 +2998,7 @@ void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb) dc->is_jmp = DISAS_NEXT; dc->pc = pc_start; dc->cc_op = CC_OP_DYNAMIC; + dc->cc_op_synced = 1; dc->singlestep_enabled = cs->singlestep_enabled; dc->fpcr = env->fpcr; dc->user = (env->sr & SR_S) == 0; |