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-rw-r--r--hw/intc/spapr_xive.c5
-rw-r--r--hw/intc/xics_spapr.c13
-rw-r--r--hw/ppc/spapr_irq.c45
-rw-r--r--include/hw/ppc/spapr_irq.h3
-rw-r--r--include/hw/ppc/spapr_xive.h1
5 files changed, 21 insertions, 46 deletions
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index 1811653aac..ba32d2cc5b 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -462,10 +462,10 @@ static int vmstate_spapr_xive_pre_save(void *opaque)
* Called by the sPAPR IRQ backend 'post_load' method at the machine
* level.
*/
-int spapr_xive_post_load(SpaprXive *xive, int version_id)
+static int spapr_xive_post_load(SpaprInterruptController *intc, int version_id)
{
if (kvm_irqchip_in_kernel()) {
- return kvmppc_xive_post_load(xive, version_id);
+ return kvmppc_xive_post_load(SPAPR_XIVE(intc), version_id);
}
return 0;
@@ -702,6 +702,7 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data)
sicc->set_irq = spapr_xive_set_irq;
sicc->print_info = spapr_xive_print_info;
sicc->dt = spapr_xive_dt;
+ sicc->post_load = spapr_xive_post_load;
}
static const TypeInfo spapr_xive_info = {
diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c
index 90b4d48877..4f64b9a9fc 100644
--- a/hw/intc/xics_spapr.c
+++ b/hw/intc/xics_spapr.c
@@ -395,6 +395,18 @@ static void xics_spapr_print_info(SpaprInterruptController *intc, Monitor *mon)
ics_pic_print_info(ics, mon);
}
+static int xics_spapr_post_load(SpaprInterruptController *intc, int version_id)
+{
+ if (!kvm_irqchip_in_kernel()) {
+ CPUState *cs;
+ CPU_FOREACH(cs) {
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ icp_resend(spapr_cpu_state(cpu)->icp);
+ }
+ }
+ return 0;
+}
+
static int xics_spapr_activate(SpaprInterruptController *intc, Error **errp)
{
if (kvm_enabled()) {
@@ -426,6 +438,7 @@ static void ics_spapr_class_init(ObjectClass *klass, void *data)
sicc->set_irq = xics_spapr_set_irq;
sicc->print_info = xics_spapr_print_info;
sicc->dt = xics_spapr_dt;
+ sicc->post_load = xics_spapr_post_load;
}
static const TypeInfo ics_spapr_info = {
diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c
index f70b331f44..f3d18b1dad 100644
--- a/hw/ppc/spapr_irq.c
+++ b/hw/ppc/spapr_irq.c
@@ -100,43 +100,22 @@ int spapr_irq_init_kvm(int (*fn)(SpaprInterruptController *, Error **),
* XICS IRQ backend.
*/
-static int spapr_irq_post_load_xics(SpaprMachineState *spapr, int version_id)
-{
- if (!kvm_irqchip_in_kernel()) {
- CPUState *cs;
- CPU_FOREACH(cs) {
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- icp_resend(spapr_cpu_state(cpu)->icp);
- }
- }
- return 0;
-}
-
SpaprIrq spapr_irq_xics = {
.nr_xirqs = SPAPR_NR_XIRQS,
.nr_msis = SPAPR_NR_MSIS,
.xics = true,
.xive = false,
-
- .post_load = spapr_irq_post_load_xics,
};
/*
* XIVE IRQ backend.
*/
-static int spapr_irq_post_load_xive(SpaprMachineState *spapr, int version_id)
-{
- return spapr_xive_post_load(spapr->xive, version_id);
-}
-
SpaprIrq spapr_irq_xive = {
.nr_xirqs = SPAPR_NR_XIRQS,
.nr_msis = SPAPR_NR_MSIS,
.xics = false,
.xive = true,
-
- .post_load = spapr_irq_post_load_xive,
};
/*
@@ -149,21 +128,6 @@ SpaprIrq spapr_irq_xive = {
*/
/*
- * Returns the sPAPR IRQ backend negotiated by CAS. XICS is the
- * default.
- */
-static SpaprIrq *spapr_irq_current(SpaprMachineState *spapr)
-{
- return spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT) ?
- &spapr_irq_xive : &spapr_irq_xics;
-}
-
-static int spapr_irq_post_load_dual(SpaprMachineState *spapr, int version_id)
-{
- return spapr_irq_current(spapr)->post_load(spapr, version_id);
-}
-
-/*
* Define values in sync with the XIVE and XICS backend
*/
SpaprIrq spapr_irq_dual = {
@@ -171,8 +135,6 @@ SpaprIrq spapr_irq_dual = {
.nr_msis = SPAPR_NR_MSIS,
.xics = true,
.xive = true,
-
- .post_load = spapr_irq_post_load_dual,
};
@@ -447,8 +409,11 @@ qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq)
int spapr_irq_post_load(SpaprMachineState *spapr, int version_id)
{
+ SpaprInterruptControllerClass *sicc;
+
spapr_irq_update_active_intc(spapr);
- return spapr->irq->post_load(spapr, version_id);
+ sicc = SPAPR_INTC_GET_CLASS(spapr->active_intc);
+ return sicc->post_load(spapr->active_intc, version_id);
}
void spapr_irq_reset(SpaprMachineState *spapr, Error **errp)
@@ -589,8 +554,6 @@ SpaprIrq spapr_irq_xics_legacy = {
.nr_msis = SPAPR_IRQ_XICS_LEGACY_NR_XIRQS,
.xics = true,
.xive = false,
-
- .post_load = spapr_irq_post_load_xics,
};
static void spapr_irq_register_types(void)
diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h
index e02e44624b..08173e714c 100644
--- a/include/hw/ppc/spapr_irq.h
+++ b/include/hw/ppc/spapr_irq.h
@@ -62,6 +62,7 @@ typedef struct SpaprInterruptControllerClass {
void (*print_info)(SpaprInterruptController *intc, Monitor *mon);
void (*dt)(SpaprInterruptController *intc, uint32_t nr_servers,
void *fdt, uint32_t phandle);
+ int (*post_load)(SpaprInterruptController *intc, int version_id);
} SpaprInterruptControllerClass;
void spapr_irq_update_active_intc(SpaprMachineState *spapr);
@@ -82,8 +83,6 @@ typedef struct SpaprIrq {
uint32_t nr_msis;
bool xics;
bool xive;
-
- int (*post_load)(SpaprMachineState *spapr, int version_id);
} SpaprIrq;
extern SpaprIrq spapr_irq_xics;
diff --git a/include/hw/ppc/spapr_xive.h b/include/hw/ppc/spapr_xive.h
index 64972754f9..d84bd5c229 100644
--- a/include/hw/ppc/spapr_xive.h
+++ b/include/hw/ppc/spapr_xive.h
@@ -55,7 +55,6 @@ typedef struct SpaprXive {
#define SPAPR_XIVE_BLOCK_ID 0x0
void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon);
-int spapr_xive_post_load(SpaprXive *xive, int version_id);
void spapr_xive_hcall_init(SpaprMachineState *spapr);
void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx);
generated by cgit v1.2.3 (git 2.26.2) at 2024-11-25 17:58:59 +0000