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-rw-r--r--target/riscv/cpu.c6
-rw-r--r--target/riscv/cpu.h1
-rw-r--r--target/riscv/cpu_cfg.h1
-rw-r--r--target/riscv/tcg/tcg-cpu.c26
4 files changed, 34 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ce0a3ded04..29fdd64298 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1443,6 +1443,12 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
DEFINE_PROP_END_OF_LIST(),
};
+const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
+ MULTI_EXT_CFG_BOOL("zic64b", zic64b, true),
+
+ DEFINE_PROP_END_OF_LIST(),
+};
+
/* Deprecated entries marked for future removal */
const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] = {
MULTI_EXT_CFG_BOOL("Zifencei", ext_zifencei, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 2725528bb5..bfa42a0393 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -765,6 +765,7 @@ typedef struct RISCVCPUMultiExtConfig {
extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[];
extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
+extern const RISCVCPUMultiExtConfig riscv_cpu_named_features[];
extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[];
extern Property riscv_cpu_options[];
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 2da8ac9582..350ea44e50 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -117,6 +117,7 @@ struct RISCVCPUConfig {
bool ext_smepmp;
bool rvv_ta_all_1s;
bool rvv_ma_all_1s;
+ bool zic64b;
uint32_t mvendorid;
uint64_t marchid;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index e9f980805e..f12e0620e5 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -114,6 +114,19 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
g_assert_not_reached();
}
+static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset)
+{
+ const RISCVCPUMultiExtConfig *feat;
+
+ for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) {
+ if (feat->offset == ext_offset) {
+ return true;
+ }
+ }
+
+ return false;
+}
+
static void cpu_bump_multi_ext_priv_ver(CPURISCVState *env,
uint32_t ext_offset)
{
@@ -123,6 +136,10 @@ static void cpu_bump_multi_ext_priv_ver(CPURISCVState *env,
return;
}
+ if (cpu_cfg_offset_is_named_feat(ext_offset)) {
+ return;
+ }
+
ext_priv_ver = cpu_cfg_ext_get_min_version(ext_offset);
if (env->priv_ver < ext_priv_ver) {
@@ -293,6 +310,13 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
}
}
+static void riscv_cpu_update_named_features(RISCVCPU *cpu)
+{
+ cpu->cfg.zic64b = cpu->cfg.cbom_blocksize == 64 &&
+ cpu->cfg.cbop_blocksize == 64 &&
+ cpu->cfg.cboz_blocksize == 64;
+}
+
/*
* Check consistency between chosen extensions while setting
* cpu->cfg accordingly.
@@ -662,6 +686,8 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
return;
}
+ riscv_cpu_update_named_features(cpu);
+
if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) {
/*
* Enhanced PMP should only be available