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-rw-r--r--accel/kvm/kvm-all.c2
-rw-r--r--contrib/elf2dmp/main.c5
-rw-r--r--gdbstub/gdbstub.c13
-rw-r--r--target/arm/tcg/meson.build10
-rw-r--r--target/arm/tcg/translate-a64.c21
-rw-r--r--target/arm/tcg/translate.c15
6 files changed, 50 insertions, 16 deletions
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index 373d876c05..7b3da8dc3a 100644
--- a/accel/kvm/kvm-all.c
+++ b/accel/kvm/kvm-all.c
@@ -2812,7 +2812,7 @@ void kvm_flush_coalesced_mmio_buffer(void)
{
KVMState *s = kvm_state;
- if (s->coalesced_flush_in_progress) {
+ if (!s || s->coalesced_flush_in_progress) {
return;
}
diff --git a/contrib/elf2dmp/main.c b/contrib/elf2dmp/main.c
index 89f0c69ab0..6d4d18501a 100644
--- a/contrib/elf2dmp/main.c
+++ b/contrib/elf2dmp/main.c
@@ -316,6 +316,11 @@ static int fill_context(KDDEBUGGER_DATA64 *kdbg,
return 1;
}
+ if (!Prcb) {
+ eprintf("Context for CPU #%d is missing\n", i);
+ continue;
+ }
+
if (va_space_rw(vs, Prcb + kdbg->OffsetPrcbContext,
&Context, sizeof(Context), 0)) {
eprintf("Failed to read CPU #%d ContextFrame location\n", i);
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
index 6911b73c07..ce8b42eb15 100644
--- a/gdbstub/gdbstub.c
+++ b/gdbstub/gdbstub.c
@@ -2051,8 +2051,17 @@ void gdb_read_byte(uint8_t ch)
return;
}
if (runstate_is_running()) {
- /* when the CPU is running, we cannot do anything except stop
- it when receiving a char */
+ /*
+ * When the CPU is running, we cannot do anything except stop
+ * it when receiving a char. This is expected on a Ctrl-C in the
+ * gdb client. Because we are in all-stop mode, gdb sends a
+ * 0x03 byte which is not a usual packet, so we handle it specially
+ * here, but it does expect a stop reply.
+ */
+ if (ch != 0x03) {
+ warn_report("gdbstub: client sent packet while target running\n");
+ }
+ gdbserver_state.allow_stop_reply = true;
vm_stop(RUN_STATE_PAUSED);
} else
#endif
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
index bdcab56489..6fca38f2cc 100644
--- a/target/arm/tcg/meson.build
+++ b/target/arm/tcg/meson.build
@@ -1,7 +1,11 @@
-gen = [
+gen_a64 = [
+ decodetree.process('a64.decode', extra_args: ['--static-decode=disas_a64']),
decodetree.process('sve.decode', extra_args: '--decode=disas_sve'),
decodetree.process('sme.decode', extra_args: '--decode=disas_sme'),
decodetree.process('sme-fa64.decode', extra_args: '--static-decode=disas_sme_fa64'),
+]
+
+gen_a32 = [
decodetree.process('neon-shared.decode', extra_args: '--decode=disas_neon_shared'),
decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'),
decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'),
@@ -13,10 +17,10 @@ gen = [
decodetree.process('a32-uncond.decode', extra_args: '--static-decode=disas_a32_uncond'),
decodetree.process('t32.decode', extra_args: '--static-decode=disas_t32'),
decodetree.process('t16.decode', extra_args: ['-w', '16', '--static-decode=disas_t16']),
- decodetree.process('a64.decode', extra_args: ['--static-decode=disas_a64']),
]
-arm_ss.add(gen)
+arm_ss.add(gen_a32)
+arm_ss.add(when: 'TARGET_AARCH64', if_true: gen_a64)
arm_ss.add(files(
'cpu32.c',
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index ef0c47407a..5fa1257d32 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -3004,6 +3004,9 @@ static bool trans_STGP(DisasContext *s, arg_ldstpair *a)
MemOp mop;
TCGv_i128 tmp;
+ /* STGP only comes in one size. */
+ tcg_debug_assert(a->sz == MO_64);
+
if (!dc_isar_feature(aa64_mte_insn_reg, s)) {
return false;
}
@@ -3029,13 +3032,25 @@ static bool trans_STGP(DisasContext *s, arg_ldstpair *a)
gen_helper_stg(cpu_env, dirty_addr, dirty_addr);
}
- mop = finalize_memop(s, a->sz);
- clean_addr = gen_mte_checkN(s, dirty_addr, true, false, 2 << a->sz, mop);
+ mop = finalize_memop(s, MO_64);
+ clean_addr = gen_mte_checkN(s, dirty_addr, true, false, 2 << MO_64, mop);
tcg_rt = cpu_reg(s, a->rt);
tcg_rt2 = cpu_reg(s, a->rt2);
- assert(a->sz == 3);
+ /*
+ * STGP is defined as two 8-byte memory operations and one tag operation.
+ * We implement it as one single 16-byte memory operation for convenience.
+ * Rebuild mop as for STP.
+ * TODO: The atomicity with LSE2 is stronger than required.
+ * Need a form of MO_ATOM_WITHIN16_PAIR that never requires
+ * 16-byte atomicity.
+ */
+ mop = MO_128;
+ if (s->align_mem) {
+ mop |= MO_ALIGN_8;
+ }
+ mop = finalize_memop_pair(s, mop);
tmp = tcg_temp_new_i128();
if (s->be_data == MO_LE) {
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index 13c88ba1b9..b71ac2d0d5 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -8799,7 +8799,7 @@ static bool trans_IT(DisasContext *s, arg_IT *a)
/* v8.1M CSEL/CSINC/CSNEG/CSINV */
static bool trans_CSEL(DisasContext *s, arg_CSEL *a)
{
- TCGv_i32 rn, rm, zero;
+ TCGv_i32 rn, rm;
DisasCompare c;
if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
@@ -8817,16 +8817,17 @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a)
}
/* In this insn input reg fields of 0b1111 mean "zero", not "PC" */
- zero = tcg_constant_i32(0);
+ rn = tcg_temp_new_i32();
+ rm = tcg_temp_new_i32();
if (a->rn == 15) {
- rn = zero;
+ tcg_gen_movi_i32(rn, 0);
} else {
- rn = load_reg(s, a->rn);
+ load_reg_var(s, rn, a->rn);
}
if (a->rm == 15) {
- rm = zero;
+ tcg_gen_movi_i32(rm, 0);
} else {
- rm = load_reg(s, a->rm);
+ load_reg_var(s, rm, a->rm);
}
switch (a->op) {
@@ -8846,7 +8847,7 @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a)
}
arm_test_cc(&c, a->fcond);
- tcg_gen_movcond_i32(c.cond, rn, c.value, zero, rn, rm);
+ tcg_gen_movcond_i32(c.cond, rn, c.value, tcg_constant_i32(0), rn, rm);
store_reg(s, a->rd, rn);
return true;
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-21 18:48:27 +0000