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authorIlya Leoshkevich <iii@linux.ibm.com>2023-11-06 10:31:23 +0100
committerThomas Huth <thuth@redhat.com>2023-11-07 19:27:08 +0100
commit43fecbe7a53fe8e5a6aff0d6471b1cc624e26b51 (patch)
treec8d800d904d6211f42e4ec16e58c6089e5b2f5dc /tests/tcg
parentaba2ec341c6d20c8dc3e6ecf87fa7c1a71e30c1e (diff)
tests/tcg/s390x: Test CLC with inaccessible second operand
Add a small test to prevent regressions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20231106093605.1349201-3-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
Diffstat (limited to 'tests/tcg')
-rw-r--r--tests/tcg/s390x/Makefile.target1
-rw-r--r--tests/tcg/s390x/clc.c48
2 files changed, 49 insertions, 0 deletions
diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.target
index 826f0a18e4..ccd4f4e68d 100644
--- a/tests/tcg/s390x/Makefile.target
+++ b/tests/tcg/s390x/Makefile.target
@@ -41,6 +41,7 @@ TESTS+=larl
TESTS+=mdeb
TESTS+=cgebra
TESTS+=clgebr
+TESTS+=clc
cdsg: CFLAGS+=-pthread
cdsg: LDFLAGS+=-pthread
diff --git a/tests/tcg/s390x/clc.c b/tests/tcg/s390x/clc.c
new file mode 100644
index 0000000000..e14189bd75
--- /dev/null
+++ b/tests/tcg/s390x/clc.c
@@ -0,0 +1,48 @@
+/*
+ * Test the CLC instruction.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#include <assert.h>
+#include <signal.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+static void handle_sigsegv(int sig, siginfo_t *info, void *ucontext)
+{
+ mcontext_t *mcontext = &((ucontext_t *)ucontext)->uc_mcontext;
+ if (mcontext->gregs[0] != 600) {
+ write(STDERR_FILENO, "bad r0\n", 7);
+ _exit(EXIT_FAILURE);
+ }
+ if (((mcontext->psw.mask >> 44) & 3) != 1) {
+ write(STDERR_FILENO, "bad cc\n", 7);
+ _exit(EXIT_FAILURE);
+ }
+ _exit(EXIT_SUCCESS);
+}
+
+int main(void)
+{
+ register unsigned long r0 asm("r0");
+ unsigned long mem = 42, rhs = 500;
+ struct sigaction act;
+ int err;
+
+ memset(&act, 0, sizeof(act));
+ act.sa_sigaction = handle_sigsegv;
+ act.sa_flags = SA_SIGINFO;
+ err = sigaction(SIGSEGV, &act, NULL);
+ assert(err == 0);
+
+ r0 = 100;
+ asm("algr %[r0],%[rhs]\n"
+ "clc 0(8,%[mem]),0(0)\n" /* The 2nd operand will cause a SEGV. */
+ : [r0] "+r" (r0)
+ : [mem] "r" (&mem)
+ , [rhs] "r" (rhs)
+ : "cc", "memory");
+
+ return EXIT_FAILURE;
+}