aboutsummaryrefslogtreecommitdiff
path: root/tests/tcg
diff options
context:
space:
mode:
authorSebastian Macke <sebastian@macke.de>2013-10-22 02:12:45 +0200
committerJia Liu <proljc@gmail.com>2013-11-20 21:47:46 +0800
commit14a650ec25ca93a626397783d6c6e840ec2502c6 (patch)
tree715f5d2d11e413ea02a670b281e86df2e6d07b03 /tests/tcg
parent93147a180c10b97bf9575a87e01c9a1c93e6c9ce (diff)
target-openrisc: Correct carry flag check of l.addc and l.addic test cases
The test cases did not correctly test for the carry flag. Signed-off-by: Sebastian Macke <sebastian@macke.de> Reviewed-by: Jia Liu <proljc@gmail.com> Signed-off-by: Jia Liu <proljc@gmail.com>
Diffstat (limited to 'tests/tcg')
-rw-r--r--tests/tcg/openrisc/test_addc.c8
-rw-r--r--tests/tcg/openrisc/test_addic.c10
2 files changed, 11 insertions, 7 deletions
diff --git a/tests/tcg/openrisc/test_addc.c b/tests/tcg/openrisc/test_addc.c
index 05d18f8ce5..a8f756a69b 100644
--- a/tests/tcg/openrisc/test_addc.c
+++ b/tests/tcg/openrisc/test_addc.c
@@ -7,9 +7,10 @@ int main(void)
b = 0x01;
c = 0xffffffff;
- result = 1;
+ result = 0;
__asm
- ("l.addc %0, %1, %2\n\t"
+ ("l.add r1, r1, r0\n\t" /* clear carry */
+ "l.addc %0, %1, %2\n\t"
: "=r"(a)
: "r"(b), "r"(c)
);
@@ -22,7 +23,8 @@ int main(void)
c = 0xffffffff;
result = 0x80000001;
__asm
- ("l.addc %0, %1, %2\n\t"
+ ("l.add r1, r1, r0\n\t" /* clear carry */
+ "l.addc %0, %1, %2\n\t"
"l.movhi %2, 0x7fff\n\t"
"l.ori %2, %2, 0xffff\n\t"
"l.addc %0, %1, %2\n\t"
diff --git a/tests/tcg/openrisc/test_addic.c b/tests/tcg/openrisc/test_addic.c
index 4ba7432521..857aaa1330 100644
--- a/tests/tcg/openrisc/test_addic.c
+++ b/tests/tcg/openrisc/test_addic.c
@@ -6,9 +6,10 @@ int main(void)
int result;
a = 1;
- result = 0x1;
+ result = 0x0;
__asm
- ("l.addic %0, %0, 0xffff\n\t"
+ ("l.add r1, r1, r0\n\t" /* clear carry */
+ "l.addic %0, %0, 0xffff\n\t"
: "+r"(a)
);
if (a != result) {
@@ -16,10 +17,11 @@ int main(void)
return -1;
}
- a = 0x1;
+ a = -1;
result = 0x201;
__asm
- ("l.addic %0, %0, 0xffff\n\t"
+ ("l.add r1, r1, r0\n\t" /* clear carry */
+ "l.addic %0, %0, 0x1\n\t"
"l.ori %0, r0, 0x100\n\t"
"l.addic %0, %0, 0x100\n\t"
: "+r"(a)