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authorRichard Henderson <rth@twiddle.net>2014-03-26 11:01:30 -0700
committerRichard Henderson <rth@twiddle.net>2014-04-18 16:57:37 -0700
commitf46fc4e6a953e78b283834f67bc338bd35d7d316 (patch)
treeef0b7e5062f937bdae18f9c4f5085ae6a3eacd1b /tcg/tcg-op.h
parentdf9ebea53ebc1c98217743f56c30ae3a46031bb9 (diff)
tcg: Use tcg_gen_mulu2_i32 in tcg_gen_muls2_i32
Rather than hard-coding use of mulu2_i32, allow muluh_i32. Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg/tcg-op.h')
-rw-r--r--tcg/tcg-op.h6
1 files changed, 2 insertions, 4 deletions
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 7eabf22f01..08dd09e266 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -2437,14 +2437,12 @@ static inline void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh,
tcg_gen_op3_i32(INDEX_op_mulsh_i32, rh, arg1, arg2);
tcg_gen_mov_i32(rl, t);
tcg_temp_free_i32(t);
- } else if (TCG_TARGET_REG_BITS == 32 && TCG_TARGET_HAS_mulu2_i32) {
+ } else if (TCG_TARGET_REG_BITS == 32) {
TCGv_i32 t0 = tcg_temp_new_i32();
TCGv_i32 t1 = tcg_temp_new_i32();
TCGv_i32 t2 = tcg_temp_new_i32();
TCGv_i32 t3 = tcg_temp_new_i32();
- tcg_gen_op4_i32(INDEX_op_mulu2_i32, t0, t1, arg1, arg2);
- /* Allow the optimizer room to replace mulu2 with two moves. */
- tcg_gen_op0(INDEX_op_nop);
+ tcg_gen_mulu2_i32(t0, t1, arg1, arg2);
/* Adjust for negative inputs. */
tcg_gen_sari_i32(t2, arg1, 31);
tcg_gen_sari_i32(t3, arg2, 31);