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| author | Peter Maydell <peter.maydell@linaro.org> | 2020-10-08 17:18:46 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-10-08 17:18:46 +0100 |
| commit | e64cf4d569f6461d6b9072e00d6e78d0ab8bd4a7 (patch) | |
| tree | efbcd66a45366ea73298f67075b07f7cd203c269 /tcg/optimize.c | |
| parent | a1d22c668a7662289b42624fe2aa92c9a23df1d2 (diff) | |
| parent | 62475e9d007d83db4d0a6ccebcda8914f392e9c9 (diff) | |
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20201008' into staging
Extend maximum gvec vector size
Fix i386 avx2 dupi
Fix mips host user-only write detection
Misc cleanups.
# gpg: Signature made Thu 08 Oct 2020 13:55:22 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth/tags/pull-tcg-20201008:
accel/tcg: Fix computing of is_write for MIPS
tcg: Remove TCG_TARGET_HAS_cmp_vec
tcg/optimize: Fold dup2_vec
tcg: Fix generation of dupi_vec for 32-bit host
tcg/i386: Fix dupi for avx2 32-bit hosts
tcg: Remove TCGOpDef.used
tcg: Move some TCG_CT_* bits to TCGArgConstraint bitfields
tcg: Remove TCG_CT_REG
tcg: Move sorted_args into TCGArgConstraint.sort_index
tcg: Drop union from TCGArgConstraint
tcg: Adjust simd_desc size encoding
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tcg/optimize.c')
| -rw-r--r-- | tcg/optimize.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/tcg/optimize.c b/tcg/optimize.c index 53aa8e5329..220f4601d5 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1109,6 +1109,21 @@ void tcg_optimize(TCGContext *s) } goto do_default; + case INDEX_op_dup2_vec: + assert(TCG_TARGET_REG_BITS == 32); + if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { + tmp = arg_info(op->args[1])->val; + if (tmp == arg_info(op->args[2])->val) { + tcg_opt_gen_movi(s, op, op->args[0], tmp); + break; + } + } else if (args_are_copies(op->args[1], op->args[2])) { + op->opc = INDEX_op_dup_vec; + TCGOP_VECE(op) = MO_32; + nb_iargs = 1; + } + goto do_default; + CASE_OP_32_64(not): CASE_OP_32_64(neg): CASE_OP_32_64(ext8s): |