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authorRichard Henderson <richard.henderson@linaro.org>2021-08-06 11:30:35 -1000
committerRichard Henderson <richard.henderson@linaro.org>2023-05-25 13:57:51 +0000
commit1d159e64cca6497565cdcbb0a8383fc8568b4983 (patch)
tree006018e0070f18d0d7a9f9db0351c753abd477a1 /tcg/mips/tcg-target.c.inc
parent4316de32e71ae2626bbf8483a0265c61d3e3a05f (diff)
tcg/mips: Try tb-relative addresses in tcg_out_movi
These addresses are often loaded by the qemu_ld/st slow path, for loading the retaddr value. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/mips/tcg-target.c.inc')
-rw-r--r--tcg/mips/tcg-target.c.inc13
1 files changed, 13 insertions, 0 deletions
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 068deab8c9..9fab424ecc 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -568,6 +568,8 @@ static void tcg_out_movi_pool(TCGContext *s, TCGReg ret,
static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
tcg_target_long arg, TCGReg tbreg)
{
+ tcg_target_long tmp;
+
if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
arg = (int32_t)arg;
}
@@ -578,6 +580,17 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
}
assert(TCG_TARGET_REG_BITS == 64);
+ /* Load addresses within 2GB of TB with 1 or 3 insns. */
+ tmp = tcg_tbrel_diff(s, (void *)arg);
+ if (tmp == (int16_t)tmp) {
+ tcg_out_opc_imm(s, OPC_DADDIU, ret, tbreg, tmp);
+ return;
+ }
+ if (tcg_out_movi_two(s, ret, tmp)) {
+ tcg_out_opc_reg(s, OPC_DADDU, ret, ret, tbreg);
+ return;
+ }
+
/* Otherwise, put 64-bit constants into the constant pool. */
tcg_out_movi_pool(s, ret, arg, tbreg);
}