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authorPaolo Bonzini <pbonzini@redhat.com>2024-07-03 13:42:49 +0200
committerPaolo Bonzini <pbonzini@redhat.com>2024-11-07 16:54:01 +0100
commit78be258c0eeba3d5613c37888889e84f2ba9bd94 (patch)
tree6ead0b7f082469df799467024026022ee7964481 /target
parenta1dacb66915eb7d08a0596cc97068a37c39930d3 (diff)
target/i386: add sha512, sm3, sm4 feature bits
SHA512, SM3, SM4 (CPUID[EAX=7,ECX=1).EAX bits 0 to 2) is supported by Clearwater Forest processor, add it to QEMU as it does not need any specific enablement. See https://lore.kernel.org/kvm/20241105054825.870939-1-tao1.su@linux.intel.com/ for reference. Reviewed-by: Tao Su <tao1.su@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target')
-rw-r--r--target/i386/cpu.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 58c96eafea..3725dbbc4b 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1116,7 +1116,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
[FEAT_7_1_EAX] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
- NULL, NULL, NULL, NULL,
+ "sha512", "sm3", "sm4", NULL,
"avx-vnni", "avx512-bf16", NULL, "cmpccxadd",
NULL, NULL, "fzrm", "fsrs",
"fsrc", NULL, NULL, NULL,