diff options
| author | Song Gao <gaosong@loongson.cn> | 2023-09-14 10:26:05 +0800 |
|---|---|---|
| committer | Song Gao <gaosong@loongson.cn> | 2023-09-20 11:43:12 +0800 |
| commit | 760f9647171bf9e1c67bc15683ee3eec6d559065 (patch) | |
| tree | e2b852a1bee4d58255f232f7440f404fd71a9218 /target | |
| parent | 342004214bf30bc2e33cb77339777d5e9ca86ea0 (diff) | |
target/loongarch: Implement xvneg
This patch includes:
- XVNEG.{B/H/W/D}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914022645.1151356-18-gaosong@loongson.cn>
Diffstat (limited to 'target')
| -rw-r--r-- | target/loongarch/disas.c | 10 | ||||
| -rw-r--r-- | target/loongarch/insn_trans/trans_vec.c.inc | 19 | ||||
| -rw-r--r-- | target/loongarch/insns.decode | 5 |
3 files changed, 30 insertions, 4 deletions
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c index 20df9c7c99..a7455840a0 100644 --- a/target/loongarch/disas.c +++ b/target/loongarch/disas.c @@ -1718,6 +1718,11 @@ static void output_vv_i_x(DisasContext *ctx, arg_vv_i *a, const char *mnemonic) output(ctx, mnemonic, "x%d, x%d, 0x%x", a->vd, a->vj, a->imm); } +static void output_vv_x(DisasContext *ctx, arg_vv *a, const char *mnemonic) +{ + output(ctx, mnemonic, "x%d, x%d", a->vd, a->vj); +} + INSN_LASX(xvadd_b, vvv) INSN_LASX(xvadd_h, vvv) INSN_LASX(xvadd_w, vvv) @@ -1738,6 +1743,11 @@ INSN_LASX(xvsubi_hu, vv_i) INSN_LASX(xvsubi_wu, vv_i) INSN_LASX(xvsubi_du, vv_i) +INSN_LASX(xvneg_b, vv) +INSN_LASX(xvneg_h, vv) +INSN_LASX(xvneg_w, vv) +INSN_LASX(xvneg_d, vv) + INSN_LASX(xvreplgr2vr_b, vr) INSN_LASX(xvreplgr2vr_h, vr) INSN_LASX(xvreplgr2vr_w, vr) diff --git a/target/loongarch/insn_trans/trans_vec.c.inc b/target/loongarch/insn_trans/trans_vec.c.inc index 689db12d71..f837d695d1 100644 --- a/target/loongarch/insn_trans/trans_vec.c.inc +++ b/target/loongarch/insn_trans/trans_vec.c.inc @@ -223,6 +223,10 @@ static bool gvec_vv_vl(DisasContext *ctx, arg_vv *a, uint32_t vd_ofs = vec_full_offset(a->vd); uint32_t vj_ofs = vec_full_offset(a->vj); + if (!check_vec(ctx, oprsz)) { + return true; + } + func(mop, vd_ofs, vj_ofs, oprsz, ctx->vl / 8); return true; } @@ -232,13 +236,16 @@ static bool gvec_vv(DisasContext *ctx, arg_vv *a, MemOp mop, void (*func)(unsigned, uint32_t, uint32_t, uint32_t, uint32_t)) { - if (!check_vec(ctx, 16)) { - return true; - } - return gvec_vv_vl(ctx, a, 16, mop, func); } +static bool gvec_xx(DisasContext *ctx, arg_vv *a, MemOp mop, + void (*func)(unsigned, uint32_t, uint32_t, + uint32_t, uint32_t)) +{ + return gvec_vv_vl(ctx, a, 32, mop, func); +} + static bool gvec_vv_i_vl(DisasContext *ctx, arg_vv_i *a, uint32_t oprsz, MemOp mop, void (*func)(unsigned, uint32_t, uint32_t, @@ -383,6 +390,10 @@ TRANS(vneg_b, LSX, gvec_vv, MO_8, tcg_gen_gvec_neg) TRANS(vneg_h, LSX, gvec_vv, MO_16, tcg_gen_gvec_neg) TRANS(vneg_w, LSX, gvec_vv, MO_32, tcg_gen_gvec_neg) TRANS(vneg_d, LSX, gvec_vv, MO_64, tcg_gen_gvec_neg) +TRANS(xvneg_b, LASX, gvec_xx, MO_8, tcg_gen_gvec_neg) +TRANS(xvneg_h, LASX, gvec_xx, MO_16, tcg_gen_gvec_neg) +TRANS(xvneg_w, LASX, gvec_xx, MO_32, tcg_gen_gvec_neg) +TRANS(xvneg_d, LASX, gvec_xx, MO_64, tcg_gen_gvec_neg) TRANS(vsadd_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_ssadd) TRANS(vsadd_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_ssadd) diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode index c48dca70b8..759172628f 100644 --- a/target/loongarch/insns.decode +++ b/target/loongarch/insns.decode @@ -1320,6 +1320,11 @@ xvsubi_hu 0111 01101000 11001 ..... ..... ..... @vv_ui5 xvsubi_wu 0111 01101000 11010 ..... ..... ..... @vv_ui5 xvsubi_du 0111 01101000 11011 ..... ..... ..... @vv_ui5 +xvneg_b 0111 01101001 11000 01100 ..... ..... @vv +xvneg_h 0111 01101001 11000 01101 ..... ..... @vv +xvneg_w 0111 01101001 11000 01110 ..... ..... @vv +xvneg_d 0111 01101001 11000 01111 ..... ..... @vv + xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr |