diff options
author | Nicholas Piggin <npiggin@gmail.com> | 2022-02-18 08:34:14 +0100 |
---|---|---|
committer | Cédric Le Goater <clg@kaod.org> | 2022-02-18 08:34:14 +0100 |
commit | 3680e99461b6d33bd45fce9b4bd5e20475c13525 (patch) | |
tree | 9c51b1c92f2cd17af0b68aed7fa0c20bdf57cc3b /target | |
parent | 4c6cf6b295d233552fb448ed4a8b4356e18dfabb (diff) |
target/ppc: Add powerpc_reset_excp_state helper
This moves the logic to reset the QEMU exception state into its own
function.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[ clg: checkpatch fixes ]
Message-Id: <20220216102545.1808018-8-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'target')
-rw-r--r-- | target/ppc/excp_helper.c | 42 |
1 files changed, 22 insertions, 20 deletions
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 6b6ec71bc2..7499fa187f 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -360,12 +360,21 @@ static void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp, target_ulong msr, } #endif -static void powerpc_set_excp_state(PowerPCCPU *cpu, - target_ulong vector, target_ulong msr) +static void powerpc_reset_excp_state(PowerPCCPU *cpu) { CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; + /* Reset exception state */ + cs->exception_index = POWERPC_EXCP_NONE; + env->error_code = 0; +} + +static void powerpc_set_excp_state(PowerPCCPU *cpu, target_ulong vector, + target_ulong msr) +{ + CPUPPCState *env = &cpu->env; + assert((msr & env->msr_mask) == msr); /* @@ -376,21 +385,20 @@ static void powerpc_set_excp_state(PowerPCCPU *cpu, * will prevent setting of the HV bit which some exceptions might need * to do. */ + env->nip = vector; env->msr = msr; hreg_compute_hflags(env); - env->nip = vector; - /* Reset exception state */ - cs->exception_index = POWERPC_EXCP_NONE; - env->error_code = 0; - /* Reset the reservation */ - env->reserve_addr = -1; + powerpc_reset_excp_state(cpu); /* * Any interrupt is context synchronizing, check if TCG TLB needs * a delayed flush on ppc64 */ check_tlb_flush(env, false); + + /* Reset the reservation */ + env->reserve_addr = -1; } static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) @@ -471,8 +479,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) case POWERPC_EXCP_FP: if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) { trace_ppc_excp_fp_ignore(); - cs->exception_index = POWERPC_EXCP_NONE; - env->error_code = 0; + powerpc_reset_excp_state(cpu); return; } env->spr[SPR_40x_ESR] = ESR_FP; @@ -609,8 +616,7 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp) case POWERPC_EXCP_FP: if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) { trace_ppc_excp_fp_ignore(); - cs->exception_index = POWERPC_EXCP_NONE; - env->error_code = 0; + powerpc_reset_excp_state(cpu); return; } @@ -783,8 +789,7 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp) case POWERPC_EXCP_FP: if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) { trace_ppc_excp_fp_ignore(); - cs->exception_index = POWERPC_EXCP_NONE; - env->error_code = 0; + powerpc_reset_excp_state(cpu); return; } @@ -969,8 +974,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp) case POWERPC_EXCP_FP: if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) { trace_ppc_excp_fp_ignore(); - cs->exception_index = POWERPC_EXCP_NONE; - env->error_code = 0; + powerpc_reset_excp_state(cpu); return; } @@ -1168,8 +1172,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp) case POWERPC_EXCP_FP: if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) { trace_ppc_excp_fp_ignore(); - cs->exception_index = POWERPC_EXCP_NONE; - env->error_code = 0; + powerpc_reset_excp_state(cpu); return; } @@ -1406,8 +1409,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp) case POWERPC_EXCP_FP: if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) { trace_ppc_excp_fp_ignore(); - cs->exception_index = POWERPC_EXCP_NONE; - env->error_code = 0; + powerpc_reset_excp_state(cpu); return; } |