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| author | Taylor Simpson <tsimpson@quicinc.com> | 2023-03-06 18:58:28 -0800 |
|---|---|---|
| committer | Taylor Simpson <tsimpson@quicinc.com> | 2023-03-06 20:47:12 -0800 |
| commit | c2b33d0be998bf539953f1dad0aa0d1cc8d9d069 (patch) | |
| tree | 7995ae0c728bf9a415287a38c431f08d2dca3065 /target/xtensa/translate.c | |
| parent | 7b84fd04bda9aab5735cdf359c2c8e39f0a31713 (diff) | |
Hexagon (target/hexagon) Improve code gen for predicated HVX instructions
The following improvements are made for predicated HVX instructions
During gen_commit_hvx, unconditionally move the "new" value into
the dest
Don't set slot_cancelled
Remove runtime bookkeeping of which registers were updated
Reduce the cases where gen_log_vreg_write[_pair] is called
It's only needed for special operands VxxV and VyV
Remove gen_log_qreg_write
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-15-tsimpson@quicinc.com>
Diffstat (limited to 'target/xtensa/translate.c')
0 files changed, 0 insertions, 0 deletions