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authorMax Filippov <jcmvbkbc@gmail.com>2023-11-30 09:19:19 -0800
committerPhilippe Mathieu-Daudé <philmd@linaro.org>2024-01-19 12:28:59 +0100
commit5f3ebbc86da5508535c7d8e4655b1dc7ad3047fe (patch)
treea42d7521d364d327d759c2dda593bb5fe354e30a /target/xtensa/translate.c
parent396f66f99dfb405bd2a29582d043d2a6b7b37d6d (diff)
target/xtensa: use generic instruction breakpoint infrastructure
Don't embed ibreak exception generation into TB and don't invalidate TB on ibreak address change. Add CPUBreakpoint pointers to xtensa CPUArchState, use cpu_breakpoint_insert/cpu_breakpoint_remove_by_ref to manage ibreak breakpoints and provide TCGCPUOps::debug_check_breakpoint callback that recognizes valid instruction breakpoints. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20231130171920.3798954-2-jcmvbkbc@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'target/xtensa/translate.c')
-rw-r--r--target/xtensa/translate.c17
1 files changed, 0 insertions, 17 deletions
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index de89940599..87947236ca 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -1123,19 +1123,6 @@ static inline unsigned xtensa_insn_len(CPUXtensaState *env, DisasContext *dc)
return xtensa_op0_insn_len(dc, b0);
}
-static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
-{
- unsigned i;
-
- for (i = 0; i < dc->config->nibreak; ++i) {
- if ((env->sregs[IBREAKENABLE] & (1 << i)) &&
- env->sregs[IBREAKA + i] == dc->pc) {
- gen_debug_exception(dc, DEBUGCAUSE_IB);
- break;
- }
- }
-}
-
static void xtensa_tr_init_disas_context(DisasContextBase *dcbase,
CPUState *cpu)
{
@@ -1205,10 +1192,6 @@ static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
gen_set_label(label);
}
- if (dc->debug) {
- gen_ibreak_check(env, dc);
- }
-
disas_xtensa_insn(env, dc);
if (dc->icount) {