diff options
| author | Max Filippov <jcmvbkbc@gmail.com> | 2013-09-04 04:57:49 +0400 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2017-01-15 13:01:55 -0800 |
| commit | 59a71f75789fb15bac0a67a18325c4ac1acc981c (patch) | |
| tree | 65a7038c5a604017f569f5a4a39af13322cb0c74 /target/xtensa/helper.h | |
| parent | bd527a83232ce8b48dac4b8c86607ad8a7e28d98 (diff) | |
target/xtensa: refactor CCOUNT/CCOMPARE
Xtensa cores may have a register (CCOUNT) that counts core clock cycles.
It may also have a number of registers (CCOMPAREx); when CCOUNT value
passes the value of CCOMPAREx, timer interrupt x is raised.
Currently xtensa target counts a number of completed instructions and
assumes that for CCOUNT one instruction takes one cycle to complete.
It calls helper function to update CCOUNT register at every TB end and
raise timer interrupts. This scheme works very predictably and doesn't
have noticeable performance impact, but it is hard to use with multiple
synchronized processors, especially with coming MTTCG.
Derive CCOUNT from the virtual simulation time, QEMU_CLOCK_VIRTUAL.
Use native QEMU timers for CCOMPARE timers, one timer for each register.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target/xtensa/helper.h')
| -rw-r--r-- | target/xtensa/helper.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/target/xtensa/helper.h b/target/xtensa/helper.h index 5ea9c5beec..427bdc7a3a 100644 --- a/target/xtensa/helper.h +++ b/target/xtensa/helper.h @@ -18,8 +18,9 @@ DEF_HELPER_1(simcall, void, env) DEF_HELPER_1(dump_state, void, env) DEF_HELPER_3(waiti, void, env, i32, i32) -DEF_HELPER_3(timer_irq, void, env, i32, i32) -DEF_HELPER_2(advance_ccount, void, env, i32) +DEF_HELPER_1(update_ccount, void, env) +DEF_HELPER_2(wsr_ccount, void, env, i32) +DEF_HELPER_2(update_ccompare, void, env, i32) DEF_HELPER_1(check_interrupts, void, env) DEF_HELPER_3(check_atomctl, void, env, i32, i32) |