diff options
| author | Max Filippov <jcmvbkbc@gmail.com> | 2011-11-26 15:48:41 +0400 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2017-01-16 19:19:03 -0800 |
| commit | 3a3c9dc4ca2eaa612cbd5d4c85d674b15eadfb02 (patch) | |
| tree | d64a088bd5188f6b19fe1fcd341283140f5fcc0e /target/xtensa/cpu.h | |
| parent | 8b912ff033cbc2e58476dfdc00fa2b8529c9eb96 (diff) | |
target-xtensa: implement RER/WER instructions
RER and WER are privileged instructions for accessing external
registers. External register address space is local to processor core.
There's no alignment requirements, addressable units are 32-bit wide
registers.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target/xtensa/cpu.h')
| -rw-r--r-- | target/xtensa/cpu.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 9a130bdabf..7e7131a596 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -103,6 +103,7 @@ enum { XTENSA_OPTION_PROCESSOR_ID, XTENSA_OPTION_DEBUG, XTENSA_OPTION_TRACE_PORT, + XTENSA_OPTION_EXTERN_REGS, }; enum { @@ -393,6 +394,8 @@ typedef struct CPUXtensaState { xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE]; unsigned autorefill_idx; bool runstall; + AddressSpace *address_space_er; + MemoryRegion *system_er; int pending_irq_level; /* level of last raised IRQ */ void **irq_inputs; XtensaCcompareTimer ccompare[MAX_NCCOMPARE]; @@ -488,6 +491,10 @@ int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, void reset_mmu(CPUXtensaState *env); void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env); void debug_exception_env(CPUXtensaState *new_env, uint32_t cause); +static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env) +{ + return env->system_er; +} static inline void xtensa_select_static_vectors(CPUXtensaState *env, unsigned n) |