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| author | Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 2021-05-19 15:29:17 +0100 |
|---|---|---|
| committer | Laurent Vivier <laurent@vivier.eu> | 2021-05-26 20:45:18 +0200 |
| commit | 5e50c6c72bf8575f124ec9397411f4a2ff0d0206 (patch) | |
| tree | 55651406bbf6c39962c5405995c00f1bd1b21a58 /target/tricore/cpu-qom.h | |
| parent | 456a0e3b3c723d1d599d73920e98474ca9073386 (diff) | |
target/m68k: implement m68k "any instruction" trace mode
The m68k trace mode is controlled by the top 2 bits in the SR register. Implement
the m68k "any instruction" trace mode where bit T1=1 and bit T0=0 in which the CPU
generates an EXCP_TRACE exception (vector 9 or offset 0x24) after executing each
instruction.
This functionality is used by the NetBSD kernel debugger to allow single-stepping
on m68k architectures.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210519142917.16693-5-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Diffstat (limited to 'target/tricore/cpu-qom.h')
0 files changed, 0 insertions, 0 deletions