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| author | TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com> | 2024-09-19 13:50:45 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-10-30 11:22:07 +1000 |
| commit | 58597bfeab45be303a4e514ce375e56b1b0c627e (patch) | |
| tree | 98fbabbe3990819b1ea5bb3344ba416c76ef9f69 /target/riscv/xthead.decode | |
| parent | 870589dcddcc542d88c5f0cdd9b2b43becc8a070 (diff) | |
target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
Ensure mcause high bit is correctly set by using 32-bit width for RV32
mode and 64-bit width for RV64 mode.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240919055048.562-6-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/xthead.decode')
0 files changed, 0 insertions, 0 deletions