diff options
| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-02-21 17:10:09 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-03-01 17:07:59 -0800 |
| commit | b8e1f32cda7805236c2bd497106a9356431c2d60 (patch) | |
| tree | 9371f41a7a6c5c75c37b9998024eb8c32d7ef7e2 /target/riscv/translate.c | |
| parent | b7fa70e2afa6c784f21f749572ce78f6467666fd (diff) | |
target/riscv: Add support for Zicond extension
The spec can be found in https://github.com/riscv/riscv-zicond.
Two instructions are added:
- czero.eqz: Moves zero to a register rd, if the condition rs2 is
equal to zero, otherwise moves rs1 to rd.
- czero.nez: Moves zero to a register rd, if the condition rs2 is
nonzero, otherwise moves rs1 to rd.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-ID: <20230221091009.36545-1-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'target/riscv/translate.c')
| -rw-r--r-- | target/riscv/translate.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 8ffa2116e0..4a957a50b5 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1103,6 +1103,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) #include "insn_trans/trans_rvh.c.inc" #include "insn_trans/trans_rvv.c.inc" #include "insn_trans/trans_rvb.c.inc" +#include "insn_trans/trans_rvzicond.c.inc" #include "insn_trans/trans_rvzawrs.c.inc" #include "insn_trans/trans_rvzfh.c.inc" #include "insn_trans/trans_rvk.c.inc" |