diff options
| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-05-26 15:21:22 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-06-13 17:36:16 +1000 |
| commit | 227fb82f99ac2d147c15342b2c83c7f6c28f20d2 (patch) | |
| tree | 1b74db1a42167e6e49f5200798975b162dbd9476 /target/riscv/translate.c | |
| parent | 022c7550d994496d38c035e2290f9f8979065bad (diff) | |
target/riscv: Use true diff for gen_pc_plus_diff
Reduce reliance on absolute values by using true pc difference for
gen_pc_plus_diff() to prepare for PC-relative translation.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230526072124.298466-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/translate.c')
| -rw-r--r-- | target/riscv/translate.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index eda022d10b..7fb4cbe84c 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -226,8 +226,10 @@ static void decode_save_opc(DisasContext *ctx) } static void gen_pc_plus_diff(TCGv target, DisasContext *ctx, - target_ulong dest) + target_long diff) { + target_ulong dest = ctx->base.pc_next + diff; + if (get_xl(ctx) == MXL_RV32) { dest = (int32_t)dest; } @@ -236,7 +238,7 @@ static void gen_pc_plus_diff(TCGv target, DisasContext *ctx, static void gen_update_pc(DisasContext *ctx, target_long diff) { - gen_pc_plus_diff(cpu_pc, ctx, ctx->base.pc_next + diff); + gen_pc_plus_diff(cpu_pc, ctx, diff); } static void generate_exception(DisasContext *ctx, int excp) @@ -547,14 +549,11 @@ static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t) static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) { - target_ulong next_pc; - /* check misaligned: */ - next_pc = ctx->base.pc_next + imm; if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) { - if ((next_pc & 0x3) != 0) { + if ((imm & 0x3) != 0) { TCGv target_pc = tcg_temp_new(); - gen_pc_plus_diff(target_pc, ctx, next_pc); + gen_pc_plus_diff(target_pc, ctx, imm); gen_exception_inst_addr_mis(ctx, target_pc); return; } |