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path: root/target/riscv/translate.c
AgeCommit message (Expand)Author
2024-04-09target/riscv: Use insn_start from DisasContextBaseRichard Henderson
2024-03-22target/riscv: enable 'vstart_eq_zero' in the end of insnsIvan Klokov
2024-03-08RISC-V: Add support for ZtsoPalmer Dabbelt
2024-02-09target/riscv: Move misa_mxl_max to classAkihiko Odaki
2024-01-29target: Use vaddr in gen_intermediate_codeAnton Johansson
2024-01-10target/riscv: Add support for Zacas extensionWeiwei Li
2023-10-04accel/tcg: Replace CPUState.env_ptr with cpu_env()Richard Henderson
2023-10-03tcg: Rename cpu_env to tcg_envRichard Henderson
2023-09-11target/riscv: Add Zvbc ISA extension supportLawrence Hunter
2023-07-10riscv: Add support for the Zfa extensionChristoph Müllner
2023-07-10target/riscv: Add support for Zfbfmin extensionWeiwei Li
2023-07-10target/riscv: Add additional xlen for address when MPRV=1Weiwei Li
2023-07-10target/riscv: Factor out extension tests to cpu_cfg.hChristoph Müllner
2023-06-13target/riscv: Remove pc_succ_insn from DisasContextWeiwei Li
2023-06-13target/riscv: Enable PC-relative translationWeiwei Li
2023-06-13target/riscv: Use true diff for gen_pc_plus_diffWeiwei Li
2023-06-13target/riscv: Change gen_set_pc_imm to gen_update_pcWeiwei Li
2023-06-13target/riscv: Change gen_goto_tb to work on displacementsWeiwei Li
2023-06-13target/riscv: Introduce cur_insn_len into DisasContextWeiwei Li
2023-06-13target/riscv: Fix target address to update badaddrWeiwei Li
2023-06-13target/riscv: Update check for Zca/Zcf/ZcdWeiwei Li
2023-06-05accel/tcg: Introduce translator_io_startRichard Henderson
2023-06-05tcg: Pass TCGHelperInfo to tcg_gen_callNRichard Henderson
2023-05-05target/riscv: Handle HLV, HSV via helpersRichard Henderson
2023-05-05target/riscv: Separate priv from mmu_idxFei Wu
2023-05-05target/riscv: Add a tb flags field for vstartLIU Zhiwei
2023-05-05target/riscv: Remove mstatus_hs_{fs, vs} from tb_flagsRichard Henderson
2023-05-05target/riscv: Encode the FS and VS on a normal way for tb flagsLIU Zhiwei
2023-05-05target/riscv: Extract virt enabled state from tb flagsLIU Zhiwei
2023-05-05target/riscv: Fix format for commentsWeiwei Li
2023-05-05target/riscv: Fix format for indentationWeiwei Li
2023-05-05target/riscv: Remove riscv_cpu_virt_enabled()Weiwei Li
2023-05-05target/riscv: Convert env->virt to a bool env->virt_enabledLIU Zhiwei
2023-05-05target/riscv: add support for Zcmp extensionWeiwei Li
2023-05-05target/riscv: add support for Zcb extensionWeiwei Li
2023-05-05target/riscv: add support for Zca extensionWeiwei Li
2023-03-07Merge tag 'pull-riscv-to-apply-20230306' of https://gitlab.com/palmer-dabbelt...Peter Maydell
2023-03-05target/riscv: Avoid tcg_const_*Richard Henderson
2023-03-05target/riscv: Drop tcg_temp_freeRichard Henderson
2023-03-05target/riscv: Drop temp_newRichard Henderson
2023-03-05target/riscv: Drop ftemp_newRichard Henderson
2023-03-05target/riscv: implement Zicboz extensionChristoph Muellner
2023-03-03Merge tag 'pull-riscv-to-apply-20230303' of https://gitlab.com/palmer-dabbelt...Peter Maydell
2023-03-01target/riscv: Add support for Zicond extensionWeiwei Li
2023-03-01target/riscv: Fix checking of whether instruciton at 'pc_next' spans pagesShaobo Song
2023-03-01accel/tcg: Pass max_insn to gen_intermediate_code by pointerRichard Henderson
2023-02-07target/riscv: fix for virtual instr exceptionDeepak Gupta
2023-02-07RISC-V: Adding XTheadFmv ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding T-Head FMemIdx extensionChristoph Müllner
2023-02-07RISC-V: Adding T-Head MemIdx extensionChristoph Müllner
generated by cgit v1.2.3 (git 2.26.2) at 2024-11-30 19:29:21 +0000