diff options
| author | Alistair Francis <alistair.francis@wdc.com> | 2020-11-03 20:43:29 -0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-11-09 15:08:53 -0800 |
| commit | 1c1c060aa866986ef8b7eb334abbb8c104a46e5c (patch) | |
| tree | 9870798361eec50c736fa4250b45ce357af3e622 /target/riscv/op_helper.c | |
| parent | 3e5979046f3f5f65828d3950d0c3ec9846d63715 (diff) | |
target/riscv: Remove the HS_TWO_STAGE flag
The HS_TWO_STAGE flag is no longer required as the MMU index contains
the information if we are performing a two stage access.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: f514b128b1ff0fb41c85f914cee18f905007a922.1604464950.git.alistair.francis@wdc.com
Diffstat (limited to 'target/riscv/op_helper.c')
| -rw-r--r-- | target/riscv/op_helper.c | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 548c5851ec..5759850e69 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -237,8 +237,6 @@ target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address, target_ulong pte; int mmu_idx = cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCESS_MASK; - riscv_cpu_set_two_stage_lookup(env, true); - switch (memop) { case MO_SB: pte = cpu_ldsb_mmuidx_ra(env, address, mmu_idx, GETPC()); @@ -265,8 +263,6 @@ target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address, g_assert_not_reached(); } - riscv_cpu_set_two_stage_lookup(env, false); - return pte; } @@ -287,8 +283,6 @@ void helper_hyp_store(CPURISCVState *env, target_ulong address, get_field(env->hstatus, HSTATUS_HU))) { int mmu_idx = cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCESS_MASK; - riscv_cpu_set_two_stage_lookup(env, true); - switch (memop) { case MO_SB: case MO_UB: @@ -309,8 +303,6 @@ void helper_hyp_store(CPURISCVState *env, target_ulong address, g_assert_not_reached(); } - riscv_cpu_set_two_stage_lookup(env, false); - return; } @@ -331,8 +323,6 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address, target_ulong pte; int mmu_idx = cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCESS_MASK; - riscv_cpu_set_two_stage_lookup(env, true); - switch (memop) { case MO_TEUW: pte = cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); @@ -344,8 +334,6 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address, g_assert_not_reached(); } - riscv_cpu_set_two_stage_lookup(env, false); - return pte; } |