diff options
author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-04-23 10:35:04 +0800 |
---|---|---|
committer | Alistair Francis <alistair.francis@wdc.com> | 2022-04-29 10:47:45 +1000 |
commit | 387e5d92713b7d85f1d077466ac0a21d7f985858 (patch) | |
tree | f6e6a097f82ce21e892960a0a36c14ee0e5219ed /target/riscv/insn32.decode | |
parent | 9e33e1753bc3a7c7cab9a293b242036344c43a02 (diff) |
target/riscv: rvk: add support for sha256 related instructions in zknh extension
- add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-9-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/insn32.decode')
-rw-r--r-- | target/riscv/insn32.decode | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 0b800b4093..db28ecdd2b 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -857,3 +857,8 @@ aes64esm 00 11011 ..... ..... 000 ..... 0110011 @r # *** RV64 Zkne/zknd Standard Extension *** aes64ks2 01 11111 ..... ..... 000 ..... 0110011 @r aes64ks1i 00 11000 1.... ..... 001 ..... 0010011 @i_aes +# *** RV32 Zknh Standard Extension *** +sha256sig0 00 01000 00010 ..... 001 ..... 0010011 @r2 +sha256sig1 00 01000 00011 ..... 001 ..... 0010011 @r2 +sha256sum0 00 01000 00000 ..... 001 ..... 0010011 @r2 +sha256sum1 00 01000 00001 ..... 001 ..... 0010011 @r2 |