diff options
| author | Tommy Wu <tommy.wu@sifive.com> | 2023-08-15 23:16:43 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-09-11 11:45:55 +1000 |
| commit | 4df282335b3b13db30123fbcca050e4bf690a9d9 (patch) | |
| tree | 0e38d7ca62ac3201bddafe55b953ae15b9f66204 /target/riscv/csr.c | |
| parent | 4e3adce1244e1ca30ec05874c3eca14911dc0825 (diff) | |
target/riscv: Align the AIA model to v1.0 ratified spec
According to the new spec, when vsiselect has a reserved value, attempts
from M-mode or HS-mode to access vsireg, or from VS-mode to access
sireg, should preferably raise an illegal instruction exception.
Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-ID: <20230816061647.600672-1-tommy.wu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/csr.c')
| -rw-r--r-- | target/riscv/csr.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 63c3b0d9fc..68eecc3c96 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1684,7 +1684,7 @@ static int rmw_iprio(target_ulong xlen, static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val, target_ulong new_val, target_ulong wr_mask) { - bool virt; + bool virt, isel_reserved; uint8_t *iprio; int ret = -EINVAL; target_ulong priv, isel, vgein; @@ -1694,6 +1694,7 @@ static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val, /* Decode register details from CSR number */ virt = false; + isel_reserved = false; switch (csrno) { case CSR_MIREG: iprio = env->miprio; @@ -1738,11 +1739,13 @@ static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val, riscv_cpu_mxl_bits(env)), val, new_val, wr_mask); } + } else { + isel_reserved = true; } done: if (ret) { - return (env->virt_enabled && virt) ? + return (env->virt_enabled && virt && !isel_reserved) ? RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; } return RISCV_EXCP_NONE; |