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authorAlistair Francis <alistair.francis@wdc.com>2020-01-31 17:03:05 -0800
committerPalmer Dabbelt <palmerdabbelt@google.com>2020-02-27 13:46:32 -0800
commit551fa7e8a695ea5fd1cca8ffd318556855bbf54f (patch)
treebacda76c80d5355e320e34e38883d54e902cb7b2 /target/riscv/cpu_bits.h
parent3067553993ae986b76a92df8a978778134ecdc84 (diff)
target/riscv: Add support for the 32-bit MSTATUSH CSR
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'target/riscv/cpu_bits.h')
-rw-r--r--target/riscv/cpu_bits.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index a24654d137..049032f2ae 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -135,6 +135,9 @@
#define CSR_MTVEC 0x305
#define CSR_MCOUNTEREN 0x306
+/* 32-bit only */
+#define CSR_MSTATUSH 0x310
+
/* Legacy Counter Setup (priv v1.9.1) */
/* Update to #define CSR_MCOUNTINHIBIT 0x320 for 1.11.0 */
#define CSR_MUCOUNTEREN 0x320