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author | LIU Zhiwei <zhiwei_liu@linux.alibaba.com> | 2023-04-12 13:43:10 +0200 |
---|---|---|
committer | Alistair Francis <alistair.francis@wdc.com> | 2023-05-05 10:49:50 +1000 |
commit | 42967f40731c197cb8e59ad8ac480a2dcc80c199 (patch) | |
tree | 267ecaf1dd4fe32e90cd7bd6fc7b0279fda2d051 /target/riscv/cpu.h | |
parent | f196639024fb460b7f5bbee39215b90b58810788 (diff) |
target/riscv: Add a general status enum for extensions
The pointer masking is the only extension that directly use status.
The vector or float extension uses the status in an indirect way.
Replace the pointer masking extension special status fields with
the general status.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20230324143031.1093-3-zhiwei_liu@linux.alibaba.com>
[rth: Add a typedef for the enum]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-3-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-3-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.h')
-rw-r--r-- | target/riscv/cpu.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index aa53d0e256..ba11279716 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -97,6 +97,14 @@ enum { TRANSLATE_G_STAGE_FAIL }; +/* Extension context status */ +typedef enum { + EXT_STATUS_DISABLED = 0, + EXT_STATUS_INITIAL, + EXT_STATUS_CLEAN, + EXT_STATUS_DIRTY, +} RISCVExtStatus; + #define MMU_USER_IDX 3 #define MAX_RISCV_PMPS (16) |