diff options
| author | LIU Zhiwei <zhiwei_liu@c-sky.com> | 2020-07-01 23:24:49 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-07-02 09:19:32 -0700 |
| commit | ad9e5aa2ae8032f19a8293b6b8f4661c06167bf0 (patch) | |
| tree | 4ec5715de24553e6f3a9c82e8e9e29586b4a267a /target/riscv/cpu.h | |
| parent | 70b78d4e71494c90d2ccb40381336bc9b9a22f79 (diff) | |
target/riscv: add vector extension field in CPURISCVState
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno, offset).
Thus elements can be directly accessed by offset from the first vector
base address.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-2-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.h')
| -rw-r--r-- | target/riscv/cpu.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 80569f0d44..0018a79fa3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -59,6 +59,7 @@ #define RVA RV('A') #define RVF RV('F') #define RVD RV('D') +#define RVV RV('V') #define RVC RV('C') #define RVS RV('S') #define RVU RV('U') @@ -88,9 +89,20 @@ typedef struct CPURISCVState CPURISCVState; #include "pmp.h" +#define RV_VLEN_MAX 512 + struct CPURISCVState { target_ulong gpr[32]; uint64_t fpr[32]; /* assume both F and D extensions */ + + /* vector coprocessor state. */ + uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); + target_ulong vxrm; + target_ulong vxsat; + target_ulong vl; + target_ulong vstart; + target_ulong vtype; + target_ulong pc; target_ulong load_res; target_ulong load_val; |