From ad9e5aa2ae8032f19a8293b6b8f4661c06167bf0 Mon Sep 17 00:00:00 2001 From: LIU Zhiwei Date: Wed, 1 Jul 2020 23:24:49 +0800 Subject: target/riscv: add vector extension field in CPURISCVState The 32 vector registers will be viewed as a continuous memory block. It avoids the convension between element index and (regno, offset). Thus elements can be directly accessed by offset from the first vector base address. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis Reviewed-by: Richard Henderson Message-Id: <20200701152549.1218-2-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'target/riscv/cpu.h') diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 80569f0d44..0018a79fa3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -59,6 +59,7 @@ #define RVA RV('A') #define RVF RV('F') #define RVD RV('D') +#define RVV RV('V') #define RVC RV('C') #define RVS RV('S') #define RVU RV('U') @@ -88,9 +89,20 @@ typedef struct CPURISCVState CPURISCVState; #include "pmp.h" +#define RV_VLEN_MAX 512 + struct CPURISCVState { target_ulong gpr[32]; uint64_t fpr[32]; /* assume both F and D extensions */ + + /* vector coprocessor state. */ + uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); + target_ulong vxrm; + target_ulong vxsat; + target_ulong vl; + target_ulong vstart; + target_ulong vtype; + target_ulong pc; target_ulong load_res; target_ulong load_val; -- cgit v1.2.3