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authorAlistair Francis <alistair.francis@wdc.com>2019-06-17 18:31:05 -0700
committerPalmer Dabbelt <palmer@sifive.com>2019-06-24 01:03:45 -0700
commit6729dbbd420696fcf69cf2c86bdfc66e072058ce (patch)
tree2c1dd04c6f40039f19ea6207bfde085660833b7f /target/riscv/cpu.h
parentc1fb65e63cfca4506a14b084afd0eca2dc464fe8 (diff)
target/riscv: Add the privledge spec version 1.11.0
Add support for the ratified RISC-V privledge spec. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv/cpu.h')
-rw-r--r--target/riscv/cpu.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5eb9cab2ad..d559d28bcd 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -81,6 +81,7 @@ enum {
#define USER_VERSION_2_02_0 0x00020200
#define PRIV_VERSION_1_09_1 0x00010901
#define PRIV_VERSION_1_10_0 0x00011000
+#define PRIV_VERSION_1_11_0 0x00011100
#define TRANSLATE_PMP_FAIL 2
#define TRANSLATE_FAIL 1