diff options
| author | Deepak Gupta <debug@rivosinc.com> | 2024-10-08 15:49:53 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-10-30 11:22:08 +1000 |
| commit | 4923f672e3d751cd8b7a10e32e09328c8f85ba1d (patch) | |
| tree | d7c83c20026866e7d8d604f0e1589f210d129bda /target/riscv/cpu.c | |
| parent | bd08b22e5648d90ed256a505da75809d0ab6be00 (diff) | |
target/riscv: Introduce elp state and enabling controls for zicfilp
zicfilp introduces a new state elp ("expected landing pad") in cpu.
During normal execution, elp is idle (NO_LP_EXPECTED) i.e not expecting
landing pad. On an indirect call, elp moves LP_EXPECTED. When elp is
LP_EXPECTED, only a subsquent landing pad instruction can set state back
to NO_LP_EXPECTED. On reset, elp is set to NO_LP_EXPECTED.
zicfilp is enabled via bit2 in *envcfg CSRs. Enabling control for M-mode
is in mseccfg CSR at bit position 10.
On trap, elp state is saved away in *status.
Adds elp to the migration state as well.
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Co-developed-by: Jim Shu <jim.shu@sifive.com>
Co-developed-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241008225010.1861630-4-debug@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.c')
| -rw-r--r-- | target/riscv/cpu.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6fa2689f35..27fbbd11b9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1011,6 +1011,9 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) env->menvcfg = 0; #endif + /* on reset elp is clear */ + env->elp = false; + env->xl = riscv_cpu_mxl(env); riscv_cpu_update_mask(env); cs->exception_index = RISCV_EXCP_NONE; |