diff options
author | Suraj Jitindar Singh <sjitindarsingh@gmail.com> | 2019-11-28 14:46:57 +0100 |
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committer | David Gibson <david@gibson.dropbear.id.au> | 2019-12-17 10:39:48 +1100 |
commit | f0ec31b1e21718b728753bcbfad54862a587050f (patch) | |
tree | 86855c0dd678f32de9264905b86246ffc7a38087 /target/ppc/timebase_helper.c | |
parent | 32d0f0d8de37519bcaa720c41f0f693b66016f1b (diff) |
target/ppc: Add SPR TBU40
The spr TBU40 is used to set the upper 40 bits of the timebase
register, present on POWER5+ and later processors.
This register can only be written by the hypervisor, and cannot be read.
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191128134700.16091-5-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc/timebase_helper.c')
-rw-r--r-- | target/ppc/timebase_helper.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c index 2395295b77..703bd9ed18 100644 --- a/target/ppc/timebase_helper.c +++ b/target/ppc/timebase_helper.c @@ -128,6 +128,11 @@ void helper_store_vtb(CPUPPCState *env, target_ulong val) cpu_ppc_store_vtb(env, val); } +void helper_store_tbu40(CPUPPCState *env, target_ulong val) +{ + cpu_ppc_store_tbu40(env, val); +} + target_ulong helper_load_40x_pit(CPUPPCState *env) { return load_40x_pit(env); |