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| author | Nicholas Piggin <npiggin@gmail.com> | 2023-06-20 23:10:41 +1000 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2023-06-25 22:41:30 +0200 |
| commit | 888050cf519eb5995424cf415f4f8f269de96824 (patch) | |
| tree | d6ff1489fd56e8fc9c586661014eeec74a634f96 /target/ppc/mmu-radix64.c | |
| parent | 6b8a05373bf142fe5fd3839c3675da005bfc9b49 (diff) | |
target/ppc: Fix instruction loading endianness in alignment interrupt
powerpc ifetch endianness depends on MSR[LE] so it has to byteswap
after cpu_ldl_code(). This corrects DSISR bits in alignment
interrupts when running in little endian mode.
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'target/ppc/mmu-radix64.c')
0 files changed, 0 insertions, 0 deletions