diff options
| author | Aditya Gupta <adityag@linux.ibm.com> | 2024-07-31 11:20:21 +0530 |
|---|---|---|
| committer | Nicholas Piggin <npiggin@gmail.com> | 2024-11-04 09:12:42 +1000 |
| commit | c0d964076c3e7fe75ea981d34cbf84612ddde663 (patch) | |
| tree | a64d0e87f60d0a1c7254a1f6d2975f38192e8a88 /target/ppc/cpu_init.h | |
| parent | ac0fbbb2d02bc68b3c0bbc873e40dc0d75e71f4d (diff) | |
target/ppc: Add Power11 DD2.0 processor
Add CPU target code to add support for new Power11 Processor.
Power11 core is same as Power10, hence reuse functions defined for
Power10.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
Tested-by: Amit Machhiwal <amachhiw@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Diffstat (limited to 'target/ppc/cpu_init.h')
| -rw-r--r-- | target/ppc/cpu_init.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/target/ppc/cpu_init.h b/target/ppc/cpu_init.h index 9e027876f3..f8fd6ff5cd 100644 --- a/target/ppc/cpu_init.h +++ b/target/ppc/cpu_init.h @@ -12,6 +12,7 @@ PPC_CILDST) #define PPC_INSNS_FLAGS_POWER10 PPC_INSNS_FLAGS_POWER9 +#define PPC_INSNS_FLAGS_POWER11 PPC_INSNS_FLAGS_POWER10 #define PPC_INSNS_FLAGS2_POWER_COMMON \ (PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | \ @@ -25,6 +26,7 @@ (PPC_INSNS_FLAGS2_POWER_COMMON | PPC2_TM) #define PPC_INSNS_FLAGS2_POWER10 \ (PPC_INSNS_FLAGS2_POWER_COMMON | PPC2_ISA310) +#define PPC_INSNS_FLAGS2_POWER11 PPC_INSNS_FLAGS2_POWER10 #define PPC_MSR_MASK_POWER_COMMON \ ((1ull << MSR_SF) | \ @@ -49,16 +51,19 @@ (PPC_MSR_MASK_POWER_COMMON | (1ull << MSR_TM)) #define PPC_MSR_MASK_POWER10 \ PPC_MSR_MASK_POWER_COMMON +#define PPC_MSR_MASK_POWER11 PPC_MSR_MASK_POWER10 #define PPC_PCR_MASK_POWER9 \ (PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07) #define PPC_PCR_MASK_POWER10 \ (PPC_PCR_MASK_POWER9 | PCR_COMPAT_3_00) +#define PPC_PCR_MASK_POWER11 PPC_PCR_MASK_POWER10 #define PPC_PCR_SUPPORTED_POWER9 \ (PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05) #define PPC_PCR_SUPPORTED_POWER10 \ (PPC_PCR_SUPPORTED_POWER9 | PCR_COMPAT_3_10) +#define PPC_PCR_SUPPORTED_POWER11 PPC_PCR_SUPPORTED_POWER10 #define PPC_LPCR_MASK_POWER9 \ (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | \ @@ -70,6 +75,7 @@ /* DD2 adds an extra HAIL bit */ #define PPC_LPCR_MASK_POWER10 \ (PPC_LPCR_MASK_POWER9 | LPCR_HAIL) +#define PPC_LPCR_MASK_POWER11 PPC_LPCR_MASK_POWER10 #define POWERPC_FLAGS_POWER_COMMON \ (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | POWERPC_FLAG_BE | \ @@ -80,5 +86,6 @@ (POWERPC_FLAGS_POWER_COMMON | POWERPC_FLAG_TM) #define POWERPC_FLAGS_POWER10 \ (POWERPC_FLAGS_POWER_COMMON | POWERPC_FLAG_BHRB) +#define POWERPC_FLAGS_POWER11 POWERPC_FLAGS_POWER10 #endif /* TARGET_PPC_CPU_INIT_H */ |