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| author | Nicholas Piggin <npiggin@gmail.com> | 2023-08-08 13:11:14 +1000 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2023-09-06 11:19:32 +0200 |
| commit | 14192307ef6e63c9a0f3c7fe937e26bee95bc6a9 (patch) | |
| tree | 5d7a00b3ab95fd16528de5a8b0139b50d470f193 /target/ppc/cpu.c | |
| parent | a11e3a1582b8c0d62ae3ef0323526baf2303e44a (diff) | |
target/ppc: Implement breakpoint debug facility for v2.07S
ISA v2.07S introduced the breakpoint facility based on the CIABR SPR.
Implement this in TCG.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'target/ppc/cpu.c')
| -rw-r--r-- | target/ppc/cpu.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c index 424f2e1741..d9c665ce18 100644 --- a/target/ppc/cpu.c +++ b/target/ppc/cpu.c @@ -102,6 +102,33 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) ppc_maybe_interrupt(env); } + +#if defined(TARGET_PPC64) +void ppc_update_ciabr(CPUPPCState *env) +{ + CPUState *cs = env_cpu(env); + target_ulong ciabr = env->spr[SPR_CIABR]; + target_ulong ciea, priv; + + ciea = ciabr & PPC_BITMASK(0, 61); + priv = ciabr & PPC_BITMASK(62, 63); + + if (env->ciabr_breakpoint) { + cpu_breakpoint_remove_by_ref(cs, env->ciabr_breakpoint); + env->ciabr_breakpoint = NULL; + } + + if (priv) { + cpu_breakpoint_insert(cs, ciea, BP_CPU, &env->ciabr_breakpoint); + } +} + +void ppc_store_ciabr(CPUPPCState *env, target_ulong val) +{ + env->spr[SPR_CIABR] = val; + ppc_update_ciabr(env); +} +#endif #endif static inline void fpscr_set_rounding_mode(CPUPPCState *env) |