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| author | Stefan Hajnoczi <stefanha@redhat.com> | 2017-05-05 16:21:00 +0100 |
|---|---|---|
| committer | Stefan Hajnoczi <stefanha@redhat.com> | 2017-05-05 16:21:16 +0100 |
| commit | 317134bb54bbaf13548c35d92cb00c650a18e32f (patch) | |
| tree | 0b9f925b0bc5b30fa7bd0fc338462c147521c193 /target/openrisc/interrupt.c | |
| parent | 4f3652b3aa5f77582c94ac434e960db242430eac (diff) | |
| parent | f4d1414a9385e3375d9107b29eeb75d27daf2147 (diff) | |
Merge remote-tracking branch 'shorne/tags/pull-or-20170504' into staging
Openrisc Features and Fixes for qemu 2.10
# gpg: Signature made Thu 04 May 2017 01:41:45 AM BST
# gpg: using RSA key 0xC3B31C2D5E6627E4
# gpg: Good signature from "Stafford Horne <shorne@gmail.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: D9C4 7354 AEF8 6C10 3A25 EFF1 C3B3 1C2D 5E66 27E4
* shorne/tags/pull-or-20170504:
target/openrisc: Support non-busy idle state using PMR SPR
target/openrisc: Remove duplicate features property
target/openrisc: Implement full vmstate serialization
migration: Add VMSTATE_STRUCT_2DARRAY()
target/openrisc: implement shadow registers
migration: Add VMSTATE_UINTTL_2DARRAY()
target/openrisc: add numcores and coreid support
target/openrisc: Fixes for memory debugging
target/openrisc: Implement EPH bit
target/openrisc: Implement EVBAR register
MAINTAINERS: Add myself as openrisc maintainer
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Diffstat (limited to 'target/openrisc/interrupt.c')
| -rw-r--r-- | target/openrisc/interrupt.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index a2eec6fb32..3959671c59 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -60,12 +60,21 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->sr |= SR_SM; env->sr &= ~SR_IEE; env->sr &= ~SR_TEE; + env->pmr &= ~PMR_DME; + env->pmr &= ~PMR_SME; env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; env->lock_addr = -1; if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) { - env->pc = (cs->exception_index << 8); + hwaddr vect_pc = cs->exception_index << 8; + if (env->cpucfgr & CPUCFGR_EVBARP) { + vect_pc |= env->evbar; + } + if (env->sr & SR_EPH) { + vect_pc |= 0xf0000000; + } + env->pc = vect_pc; } else { cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); } |