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authorPhilippe Mathieu-Daudé <f4bug@amsat.org>2020-11-24 15:17:25 +0100
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>2021-01-14 17:13:53 +0100
commitaac357ec895bfb97b6edca999d91f49b5de5049a (patch)
tree8d34d20a2c544235397520b7f081b6b3603daea3 /target/mips
parent0e9524af2dd55bee8e10896a8579b29b7746efca (diff)
target/mips: Convert Rel6 Special2 opcode to decodetree
Special2 opcode have been removed from the Release 6. Add a single decodetree entry for all the opcode class, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() call. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-7-f4bug@amsat.org>
Diffstat (limited to 'target/mips')
-rw-r--r--target/mips/mips32r6.decode2
-rw-r--r--target/mips/rel6_translate.c7
-rw-r--r--target/mips/translate.c2
3 files changed, 9 insertions, 2 deletions
diff --git a/target/mips/mips32r6.decode b/target/mips/mips32r6.decode
index d71a65f32c..dd7faf75ab 100644
--- a/target/mips/mips32r6.decode
+++ b/target/mips/mips32r6.decode
@@ -15,3 +15,5 @@
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype
LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
+
+REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2
diff --git a/target/mips/rel6_translate.c b/target/mips/rel6_translate.c
index da70ff9662..139a7524ee 100644
--- a/target/mips/rel6_translate.c
+++ b/target/mips/rel6_translate.c
@@ -18,6 +18,13 @@
#include "decode-mips32r6.c.inc"
#include "decode-mips64r6.c.inc"
+bool trans_REMOVED(DisasContext *ctx, arg_REMOVED *a)
+{
+ gen_reserved_instruction(ctx);
+
+ return true;
+}
+
static bool trans_LSA(DisasContext *ctx, arg_rtype *a)
{
return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index e3bb1e83ef..2f23ce4a36 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -27136,8 +27136,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
int rs, rt, rd;
uint32_t op1;
- check_insn_opc_removed(ctx, ISA_MIPS_R6);
-
rs = (ctx->opcode >> 21) & 0x1f;
rt = (ctx->opcode >> 16) & 0x1f;
rd = (ctx->opcode >> 11) & 0x1f;