diff options
| author | Stefan Pejic <stefan.pejic@syrmia.com> | 2022-05-04 13:03:57 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2022-06-11 11:35:22 +0200 |
| commit | a1b092537ac52b9a19e14ea163cb653149efcbb8 (patch) | |
| tree | 0cf9ab81827a0e3054473c715199584957e115a5 /target/mips | |
| parent | 1d29f899e7f2ae9bd1bc3eb0c59e72fe932f53a6 (diff) | |
target/mips: Fix emulation of nanoMIPS MTHLIP instruction
The field ac in nanoMIPS instruction MTHLIP rs, ac is specified in
nanoMIPS documentation as opcode[15..14] (2 bits). However, in the
current QEMU code, the corresponding argument passed to the helper
gen_helper_mthlip() has the value of opcode[15..11] (5 bits). Right
shift the value of this argument by three bits to fix this.
Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220504110403.613168-2-stefan.pejic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'target/mips')
| -rw-r--r-- | target/mips/tcg/nanomips_translate.c.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc index 916cece4d2..58ae35a156 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -1597,7 +1597,7 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc, check_dsp(ctx); switch (extract32(ctx->opcode, 12, 2)) { case NM_MTHLIP: - tcg_gen_movi_tl(t0, v2); + tcg_gen_movi_tl(t0, v2 >> 3); gen_helper_mthlip(t0, v0_t, cpu_env); break; case NM_SHILOV: |