diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-12-15 00:54:34 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-01-14 17:13:53 +0100 |
| commit | d7efb69382cde8f29cd37df321b399542db9fdd2 (patch) | |
| tree | d7759917d3476a791cb9089dba563507be54a68d /target/mips/translate.c | |
| parent | 311edee771510436fc70b2e4fbe5f9fd3cf3d14d (diff) | |
target/mips/translate: Expose check_mips_64() to 32-bit mode
To allow compiling 64-bit specific translation code more
generically (and removing #ifdef'ry), allow compiling
check_mips_64() on 32-bit targets.
If ever called on 32-bit, we obviously emit a reserved
instruction exception.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201215225757.764263-3-f4bug@amsat.org>
Diffstat (limited to 'target/mips/translate.c')
| -rw-r--r-- | target/mips/translate.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index d4d5d294f3..7e8afb363a 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2971,18 +2971,16 @@ static inline void check_ps(DisasContext *ctx) check_cp1_64bitmode(ctx); } -#ifdef TARGET_MIPS64 /* - * This code generates a "reserved instruction" exception if 64-bit - * instructions are not enabled. + * This code generates a "reserved instruction" exception if cpu is not + * 64-bit or 64-bit instructions are not enabled. */ void check_mips_64(DisasContext *ctx) { - if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) { + if (unlikely((TARGET_LONG_BITS != 64) || !(ctx->hflags & MIPS_HFLAG_64))) { gen_reserved_instruction(ctx); } } -#endif #ifndef CONFIG_USER_ONLY static inline void check_mvh(DisasContext *ctx) |