diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2023-05-02 10:01:56 +0100 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-05-11 09:53:41 +0100 |
| commit | 3ec02c1f0f539ea117817484f4a352010edaf9e2 (patch) | |
| tree | b31fe128d7a27c4cecf7e2a209ed53663748ab25 /target/mips/tcg | |
| parent | 94901422840c2a33e7889fd87540e65bc9028283 (diff) | |
target/mips: Add MO_ALIGN to gen_llwp, gen_scwp
These are atomic operations, so mark as requiring alignment.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/mips/tcg')
| -rw-r--r-- | target/mips/tcg/nanomips_translate.c.inc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc index 97b9572caa..e08343414c 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -998,7 +998,7 @@ static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset, TCGv tmp2 = tcg_temp_new(); gen_base_offset_addr(ctx, taddr, base, offset); - tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, MO_TEUQ | MO_ALIGN); if (cpu_is_bigendian(ctx)) { tcg_gen_extr_i64_tl(tmp2, tmp1, tval); } else { @@ -1039,7 +1039,8 @@ static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset, tcg_gen_ld_i64(llval, cpu_env, offsetof(CPUMIPSState, llval_wp)); tcg_gen_atomic_cmpxchg_i64(val, taddr, llval, tval, - eva ? MIPS_HFLAG_UM : ctx->mem_idx, MO_64); + eva ? MIPS_HFLAG_UM : ctx->mem_idx, + MO_64 | MO_ALIGN); if (reg1 != 0) { tcg_gen_movi_tl(cpu_gpr[reg1], 1); } |