diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-12-16 12:14:00 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-01-14 17:13:53 +0100 |
| commit | 13514fc93e6b2ead6e984bcd104975b6b4f375e8 (patch) | |
| tree | 0a1ea93a3afe95fdc91cdf4ae10ad69e5d3526f3 /target/mips/mips-defs.h | |
| parent | d913c3992dfd9506a8201c2995d7c910a18db92f (diff) | |
target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6
Use the single ISA_MIPS32R6 definition to check if the Release 6
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R6 in few commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-11-f4bug@amsat.org>
Diffstat (limited to 'target/mips/mips-defs.h')
| -rw-r--r-- | target/mips/mips-defs.h | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index b71127ddd7..fea547508f 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -21,7 +21,6 @@ #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS32R5 0x0000000000000800ULL #define ISA_MIPS32R6 0x0000000000002000ULL -#define ISA_MIPS64R6 0x0000000000004000ULL #define ISA_NANOMIPS32 0x0000000000008000ULL /* * bits 24-39: MIPS ASEs @@ -87,7 +86,7 @@ /* MIPS Technologies "Release 6" */ #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) -#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6) +#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6) /* Wave Computing: "nanoMIPS" */ #define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32) |