diff options
| author | James Hogan <james.hogan@imgtec.com> | 2017-07-18 12:55:49 +0100 |
|---|---|---|
| committer | Yongbok Kim <yongbok.kim@imgtec.com> | 2017-07-20 22:42:26 +0100 |
| commit | 74dbf824a1313b6064bbebb981a7440951d70896 (patch) | |
| tree | ecd1b2ca5ee642293b08e9527fbece6fa6298188 /target/mips/cpu.h | |
| parent | 9658e4c342e6ae0d775101f8f6bb6efb16789af1 (diff) | |
target/mips: Add CP0_Ebase.WG (write gate) support
Add support for the CP0_EBase.WG bit, which allows upper bits to be
written (bits 31:30 on MIPS32, or bits 63:30 on MIPS64), along with the
CP0_Config5.CV bit to control whether the exception vector for Cache
Error exceptions is forced into KSeg1.
This is necessary on MIPS32 to support Segmentation Control and Enhanced
Virtual Addressing (EVA) extensions (where KSeg1 addresses may not
represent an unmapped uncached segment).
It is also useful on MIPS64 to allow the exception base to reside in
XKPhys, and possibly out of range of KSEG0 and KSEG1.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
[yongbok.kim@imgtec.com:
minor changes]
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Diffstat (limited to 'target/mips/cpu.h')
| -rw-r--r-- | target/mips/cpu.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 4a4747af25..2b699a0e24 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -399,7 +399,9 @@ struct CPUMIPSState { #define CP0Ca_EC 2 target_ulong CP0_EPC; int32_t CP0_PRid; - int32_t CP0_EBase; + target_ulong CP0_EBase; + target_ulong CP0_EBaseWG_rw_bitmask; +#define CP0EBase_WG 11 target_ulong CP0_CMGCRBase; int32_t CP0_Config0; #define CP0C0_M 31 @@ -447,6 +449,7 @@ struct CPUMIPSState { #define CP0C3_MSAP 28 #define CP0C3_BP 27 #define CP0C3_BI 26 +#define CP0C3_SC 25 #define CP0C3_IPLW 21 #define CP0C3_MMAR 18 #define CP0C3_MCU 17 |