diff options
| author | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2018-04-14 18:58:56 +0200 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2018-04-30 16:43:20 +0200 |
| commit | 5153bb897a3d41d52c5b7187e9e40d5c26b04d57 (patch) | |
| tree | 5a86c5b35a799664617b58f64c2b4015d808386a /target/microblaze | |
| parent | 59b1a90b0b5dc6b368364e9e1d40184eb4506c39 (diff) | |
target-microblaze: Fix trap checks for FPU insns
Fix trap checks for FPU insns when extended FPU insns are enabled.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target/microblaze')
| -rw-r--r-- | target/microblaze/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index f739751930..ec12fed49d 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1412,7 +1412,7 @@ static void dec_fpu(DisasContext *dc) if ((dc->tb_flags & MSR_EE_FLAG) && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) - && (dc->cpu->cfg.use_fpu != 1)) { + && !dc->cpu->cfg.use_fpu) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); return; |