From 5153bb897a3d41d52c5b7187e9e40d5c26b04d57 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Sat, 14 Apr 2018 18:58:56 +0200 Subject: target-microblaze: Fix trap checks for FPU insns Fix trap checks for FPU insns when extended FPU insns are enabled. Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target/microblaze') diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index f739751930..ec12fed49d 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1412,7 +1412,7 @@ static void dec_fpu(DisasContext *dc) if ((dc->tb_flags & MSR_EE_FLAG) && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) - && (dc->cpu->cfg.use_fpu != 1)) { + && !dc->cpu->cfg.use_fpu) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); return; -- cgit v1.2.3