diff options
| author | Jiajie Chen <c@jia.je> | 2023-08-22 09:13:52 +0200 |
|---|---|---|
| committer | Song Gao <gaosong@loongson.cn> | 2023-08-24 11:17:57 +0800 |
| commit | c5af6628f4be5d30800233e59ba3842ca19a12e6 (patch) | |
| tree | b778ec63140afbe615fd6c9bb883030450f93e02 /target/loongarch/insn_trans/trans_lsx.c.inc | |
| parent | 34423c01941928974f4854bc23a949789154fee7 (diff) | |
target/loongarch: Extract make_address_i() helper
Signed-off-by: Jiajie Chen <c@jia.je>
Co-authored-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn>
[PMD: Extract helper from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230822071405.35386-7-philmd@linaro.org>
Diffstat (limited to 'target/loongarch/insn_trans/trans_lsx.c.inc')
| -rw-r--r-- | target/loongarch/insn_trans/trans_lsx.c.inc | 32 |
1 files changed, 8 insertions, 24 deletions
diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc b/target/loongarch/insn_trans/trans_lsx.c.inc index 875cb7d51d..50153d6d0b 100644 --- a/target/loongarch/insn_trans/trans_lsx.c.inc +++ b/target/loongarch/insn_trans/trans_lsx.c.inc @@ -4255,7 +4255,7 @@ TRANS(vextrins_d, gen_vv_i, gen_helper_vextrins_d) static bool trans_vld(DisasContext *ctx, arg_vr_i *a) { - TCGv addr, temp; + TCGv addr; TCGv_i64 rl, rh; TCGv_i128 val; @@ -4266,11 +4266,7 @@ static bool trans_vld(DisasContext *ctx, arg_vr_i *a) rl = tcg_temp_new_i64(); rh = tcg_temp_new_i64(); - if (a->imm) { - temp = tcg_temp_new(); - tcg_gen_addi_tl(temp, addr, a->imm); - addr = temp; - } + addr = make_address_i(ctx, addr, a->imm); tcg_gen_qemu_ld_i128(val, addr, ctx->mem_idx, MO_128 | MO_TE); tcg_gen_extr_i128_i64(rl, rh, val); @@ -4282,7 +4278,7 @@ static bool trans_vld(DisasContext *ctx, arg_vr_i *a) static bool trans_vst(DisasContext *ctx, arg_vr_i *a) { - TCGv addr, temp; + TCGv addr; TCGv_i128 val; TCGv_i64 ah, al; @@ -4293,11 +4289,7 @@ static bool trans_vst(DisasContext *ctx, arg_vr_i *a) ah = tcg_temp_new_i64(); al = tcg_temp_new_i64(); - if (a->imm) { - temp = tcg_temp_new(); - tcg_gen_addi_tl(temp, addr, a->imm); - addr = temp; - } + addr = make_address_i(ctx, addr, a->imm); get_vreg64(ah, a->vd, 1); get_vreg64(al, a->vd, 0); @@ -4356,7 +4348,7 @@ static bool trans_vstx(DisasContext *ctx, arg_vrr *a) #define VLDREPL(NAME, MO) \ static bool trans_## NAME (DisasContext *ctx, arg_vr_i *a) \ { \ - TCGv addr, temp; \ + TCGv addr; \ TCGv_i64 val; \ \ CHECK_SXE; \ @@ -4364,11 +4356,7 @@ static bool trans_## NAME (DisasContext *ctx, arg_vr_i *a) \ addr = gpr_src(ctx, a->rj, EXT_NONE); \ val = tcg_temp_new_i64(); \ \ - if (a->imm) { \ - temp = tcg_temp_new(); \ - tcg_gen_addi_tl(temp, addr, a->imm); \ - addr = temp; \ - } \ + addr = make_address_i(ctx, addr, a->imm); \ \ tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, MO); \ tcg_gen_gvec_dup_i64(MO, vec_full_offset(a->vd), 16, ctx->vl/8, val); \ @@ -4384,7 +4372,7 @@ VLDREPL(vldrepl_d, MO_64) #define VSTELM(NAME, MO, E) \ static bool trans_## NAME (DisasContext *ctx, arg_vr_ii *a) \ { \ - TCGv addr, temp; \ + TCGv addr; \ TCGv_i64 val; \ \ CHECK_SXE; \ @@ -4392,11 +4380,7 @@ static bool trans_## NAME (DisasContext *ctx, arg_vr_ii *a) \ addr = gpr_src(ctx, a->rj, EXT_NONE); \ val = tcg_temp_new_i64(); \ \ - if (a->imm) { \ - temp = tcg_temp_new(); \ - tcg_gen_addi_tl(temp, addr, a->imm); \ - addr = temp; \ - } \ + addr = make_address_i(ctx, addr, a->imm); \ \ tcg_gen_ld_i64(val, cpu_env, \ offsetof(CPULoongArchState, fpr[a->vd].vreg.E(a->imm2))); \ |